Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs


A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

Formal Verification Of a Sequestered Encryption Architecture


A technical paper titled “Security Verification of Low-Trust Architectures” was published by researchers at Princeton University, University of Michigan, and Lafayette College. Abstract: "Low-trust architectures work on, from the viewpoint of software, always-encrypted data, and significantly reduce the amount of hardware trust to a small software-free enclave component. In this paper, we... » read more

The Threat Of Supply Chain Insecurity


Concerns about counterfeit chips are growing as more chips are deployed in safety- and mission-critical applications, prompting better traceability and new and inexpensive solutions that can determine if chips are new or used. But some counterfeit chips still slip through, and the problem gets worse wherever there are shortages. Estimates vary widely for how much counterfeiting costs in term... » read more

New Concepts Required For Security Verification


Verification for security requires new practices in both the development and verification flows, but tools and methodologies to enable this are rudimentary today. Flows are becoming more complex, especially when they span multiple development groups. Security is special in that it is pervasive throughout the development process, requiring both positive and negative verification. Positive ver... » read more

Microarchitectural Side-Channel Attacks And Defenses on NVRAM DIMMs


A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was published by researchers at UC San Diego, Purdue University, and UT Austin. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform r... » read more

Hardware Security: Eliminating/Reducing A Blind Spot of Side Channels (CISPA Helmholtz Center for Information Security)


A technical paper titled "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channels" was published by researchers at CISPA Helmholtz Center for Information Security. Abstract: "In the last years, there has been a rapid increase in microarchitectural attacks, exploiting side effects of various parts of the CPU. Most of them have in common that they rely ... » read more

Secure Implementation Of Post-Quantum Crypto In The Spotlight


The US-based NIST body takes a leading role in the migration to Post-Quantum Crypto (PQC). After a multi-year selection process, in 2022 they preliminarily identified a number of Post Quantum algorithms, which were recommended to replace the current public key algorithms (RSA, ECC). While the process of scrutiny is still ongoing, they now took another important step by putting emphasis on imple... » read more

What’s Required To Secure Chips


Experts at the Table: Semiconductor Engineering sat down to talk about how to verify that a semiconductor design will be secure, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker Verification. ... » read more

Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM


A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was written (preprint) by researchers at UC San Diego, UT Austin, and Purdue University. Abstract "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as implemented by the Intel Optane... » read more

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