tag: Siemens EDA

Is PPA Relevant Today?
By Brian Bailey - 12 Sep, 2024 - Comments: 1

The optimization of power, performance, and area (PPA) has been at the core of chip design since the dawn of EDA, but these metrics are becoming less valuable without the context of how and where these chips will be used. Unlike in the past, however, that context now comes from factors outside of hardware development. And while PPA still serves as a useful proxy for many parts of the hardwar... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips
By Adam Kovac - 12 Sep, 2024 - Comments: 0

Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

On Analysis Of RDC Issues For Identifying Reset Tree Design Bugs And Further Strategies For Noise Reduction
By Siemens EDA - 12 Sep, 2024 - Comments: 0

Reset tree checks should be viewed thoroughly before reset domain crossing analysis. Static verification tools have many checks for reset tree analysis. This paper discusses the usage of non-resettable registers (NRRs) in reset paths. NRRs can cause metastability in the reset paths and hence thorough verification is a must. The paper discusses reduction of false failure reporting noise strategi... » read more

Blog Review: Sept. 11
By Jesse Allen - 11 Sep, 2024 - Comments: 0

Cadence's Neha Joshi introduces the IEEE 1801 standard, also known as UPF (Unified Power Format), which offers a uniform framework for defining power domains, power states, and power intent to ensure consistency across diverse tools and phases of the design process. Siemens' John McMillan warns that known good die may not behave the same in 3D-ICs as they do standalone and suggests that mult... » read more

Striking A Balance On Efficiency, Performance, And Cost
By Ed Sperling - 11 Sep, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power-related issues such as voltage droop, application-specific processing elements, the impact of physical effects in advanced packaging, and the benefits of backside power delivery, with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product m... » read more

Standardizing Defect Coverage In Analog/Mixed Signal Test
By Gregory Haley - 10 Sep, 2024 - Comments: 0

A newly drafted IEEE standard will bring more consistency to defect metrics in analog/mixed (AMS) designs, a long-overdue step that has become too difficult to ignore in the costly heterogeneous assemblies being deployed inside of data centers and mobile devices. Standardizing analog is no simple feat due to the legacy approach to AMS design, and this is not the first attempt at improving te... » read more

Balancing Programmability And Performance In Cars
By Ann Mutschler - 05 Sep, 2024 - Comments: 0

The rate of change in the automotive industry is accelerating with the shift toward software-defined vehicles and ongoing advancements in algorithms and chip architectures. The challenge now is to figure out the best way to prevent rapid obsolescence, improve safety, and keep the cost of these changes to a minimum. Today, updatable automotive hardware is typically achieved through FPGAs, but... » read more

Photonics Could Reduce The Cost Of Lidar
By Karen Heyman - 05 Sep, 2024 - Comments: 0

Using light to move data over shorter distances is becoming more common, both because there is much more data to move around and because photons are faster and cooler than electrons. Using optical fiber for mission-critical communication is already well established. It has been the preferred PHY for long-haul communications for decades because it doesn’t suffer from the attenuation losses ... » read more

Blog Review: Sept. 4
By Jesse Allen - 04 Sep, 2024 - Comments: 0

Synopsys' Jyotika Athavale and Randy Fish sit down with Google's Rama Govindaraju and Microsoft's Robert S. Chappell to discuss silent data corruption and why a solution will require chip designers and manufacturers, software and hardware engineers, vendors, and anyone involved in computer data to collaborate and take the issue seriously. Siemens' Karen Chow and Joel Mercier explain the rela... » read more

Design Optimal ESD Protection With Context-Aware SPICE Simulation
By Neel Natekar - 29 Aug, 2024 - Comments: 0

Electrostatic discharge (ESD) is a major reliability concern for modern ICs. Ensuring the robustness of ICs in an ESD event by providing adequate ESD protection is proving to be a major challenge for IC designers due to factors such as shrinking of the design features, reduction in gate oxide thickness, increase in the contact and interconnect resistance and an increase in the overall design co... » read more

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