tag: Siemens EDA

Blog Review: May 22
By Jesse Allen - 22 May, 2024 - Comments: 0

Cadence's Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens' Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain spec... » read more

High-Level Synthesis Propels Next-Gen AI Accelerators
By Russell Klein - 20 May, 2024 - Comments: 0

Everything around you is getting smarter. Artificial intelligence is not just a data center application but will be deployed in all kinds of embedded systems that we interact with daily. We expect to talk to and gesture at them. We expect them to recognize and understand us. And we expect them to operate with just a little bit of common sense. This intelligence is making these systems not just ... » read more

Chip Aging Becoming Key Factor In Data Center Economics
By Ann Mutschler - 20 May, 2024 - Comments: 1

Chip aging is becoming a much bigger concern inside of data centers, where it can impact server uptime, utilization rates, and the amount of energy needed to drive signals and cool entire server racks. Aging in chips is the result of both higher logic utilization and increasing transistor density. This is problematic for data centers, in general, but especially for AI chips where digital log... » read more

Will Domain-Specific ICs Become Ubiquitous?
By Brian Bailey - 16 May, 2024 - Comments: 0

Questions are surfacing for all types of design, ranging from small microcontrollers to leading-edge chips, over whether domain-specific design will become ubiquitous, or whether it will fall into the historic pattern of customization first, followed by lower-cost, general-purpose components. Custom hardware always has been a double-edged sword. It can provide a competitive edge for chipmake... » read more

Running More Efficient AI/ML Code With Neuromorphic Engines
By Karen Heyman - 16 May, 2024 - Comments: 0

Neuromorphic engineering is finally getting closer to market reality, propelled by the AI/ML-driven need for low-power, high-performance solutions. Whether current initiatives result in true neuromorphic devices, or whether devices will be inspired by neuromorphic concepts, remains to be seen. But academic and industry researchers continue to experiment in the hopes of achieving significant ... » read more

Power/Performance Costs In Chip Security
By Adam Kovac - 16 May, 2024 - Comments: 0

Hackers ranging from hobbyists to corporate spies and nation states are continually poking and prodding for weaknesses in data centers, cars, personal computers, and every other electronic device, resulting in a growing effort to build security into chips and electronic systems. The current estimate is that 60% of chips and systems have some type of security built in, and that percentage is ... » read more

High-Level Synthesis Enables The Next Generation Of Edge AI Accelerators
By Siemens EDA - 15 May, 2024 - Comments: 0

AI is becoming pervasive. But the ever increasing complexity is a challenge for IoT systems. Achieving the highest levels of performance and efficiency in edge AI means going beyond software and off the shelf hardware. Bespoke hardware accelerators in FPGA or ASICs can deliver much higher performance while consuming less energy. Building these accelerators with High-Level Synthesis slashes desi... » read more

Blog Review: May 15
By Jesse Allen - 15 May, 2024 - Comments: 0

Cadence's Anika Sunda suggests that RISC-V has opened numerous doors for innovation and believes EDA tools can help bridge the knowledge gap and foster a growing community of RISC-V developers. Synopsys' Alessandra Costa chats with industry experts about challenges facing analog design, what's needed for multi-die designs, and the potential of AI. Siemens' Bill Ji explains why understandi... » read more

Reset Domain Crossing Verification
By Reetika - 13 May, 2024 - Comments: 0

By Reetika and Sulabh Kumar Khare To meet low-power and high-performance requirements, system on chip (SoC) designs are equipped with several asynchronous and soft reset signals. These reset signals help to safeguard software and hardware functional safety as they can be asserted to speedily recover the system onboard to an initial state and clear any pending errors or events. By definiti... » read more

SRAM Security Concerns Grow
By Karen Heyman - 09 May, 2024 - Comments: 0

SRAM security concerns are intensifying as a combination of new and existing techniques allow hackers to tap into data for longer periods of time after a device is powered down. This is particularly alarming as the leading edge of design shifts from planar SoCs to heterogeneous systems in package, such as those used in AI or edge processing, where chiplets frequently have their own memory hi... » read more

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