Engineering After Orthogonalization: Why Verification Has Become A Lifecycle Discipline


Over the past several decades studying verification practices across the semiconductor industry, I’ve watched assumptions that once held up remarkably well begin to strain under the weight of modern system complexity. This is not a loss of engineering rigor. It is the result of systems that no longer conform to the boundaries earlier design models depended on. For much of the industry’s ... » read more

How And Why To Optimize NPUs


Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones.  Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven... » read more

Liquid Cooling Gains Traction In Data Centers


All electronics generate heat, and that heat must be removed to ensure those electronics don’t overheat. Moving air has been the predominant approach for decades, with liquid cooling limited to particularly intense computing workloads, largely in the supercomputing domain. With the rise in AI, data-center power density has grown to the point where liquid cooling is now seeing a larger buil... » read more

Will 2026 Be Dominated By AI?


Many opportunities and problems became highly interlinked in 2025, fueled by the historic growth in everything AI. But how close are we coming to breaking points, and what are people doing to mitigate them? That is the story that will unfold this year. AI's penetration into an increasing number of workloads is placing almost quadratic demands on compute, memory, interconnect, and the archite... » read more

Blog Review: Jan. 14


Arm's Paul Black demonstrates how lightweight LLVM sanitizers help detect undefined behavior, improve code quality, and expose hidden bugs in embedded C and C++ projects, with a focus on two sanitizers that can catch issues such as unsigned signed shift overflows, array overflows, and stack corruption. Imagination's Alex Pim provides an overview of LLM inference acceleration for mobile and e... » read more

Why Scan Diagnosis Should Be Part Of Every Fabless Company’s Yield Playbook


A fabless semiconductor company's world spins around two things, pushing design differentiation and getting those designs to market quickly and profitably. Yield isn’t just a manufacturing KPI. It's a business lever. And one of the most under-used levers in modern fabs is scan diagnosis, the practice of turning deterministic test infrastructure and failing test data into precise and action... » read more

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL


High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this code to RTL, which can be input to the traditional RTL downstream flow (RTL/GDS). Formally checking generated RTL can be difficult to analyze, as errors cannot be correlated to the HLS source code. ... » read more

Is End-To-End Security Possible?


Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Automotive Outlook: 2026


The automotive industry stands at a crossroads entering 2026, facing a complex interplay of global tariffs, evolving electric vehicle (EV) dynamics, and the infusion of AI into just about everything. As manufacturers and suppliers navigate recent financing shifts and regulatory changes, they also must address consumer concerns over EV affordability and range, OEM concerns over when to develo... » read more

Formal Verification Of Synthesizable C++/SystemC Designs


Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL. High-level synthesis (HLS) is a design flow in which design intent is des... » read more

← Older posts Newer posts →