tag: Siemens EDA

Does Your RISC-V Core Meet The Standard?
By Brian Bailey - 29 Jan, 2026 - Comments: 0

Key Takeaways Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables flexibility, there is a potential for ecosystem fragmentation. It is mathematically impossible to test every instruction combination, so engineers are moving beyond just "bl... » read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier
By Ann Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

AI’s Impact On Engineering Jobs May Be Different Than Expected
By Liz Allan - 29 Jan, 2026 - Comments: 0

Key Takeaways: AI is expected to eliminate many repetitive, entry-level tasks, but that may allow engineering students trained on the latest tools to start in more senior positions. AI is a force multiplier. It can accelerate the learning curve for junior engineers. While AI is very good at solving multi-dimensional problems, domain expertise, critical thinking, and sanity checks wil... » read more

Blog Review: Jan. 28
By Jesse Allen - 28 Jan, 2026 - Comments: 0

Synopsys' Dana Neustadter and Vincent van der Leest argue that a hardware-based approach to security is required to fully address the risks introduced by modern AI architectures and the distributed workloads they support. Siemens EDA's Tova Levy examines multiphysics challenges in 3D-IC designs and outlines three design imperatives to identify risks earlier and support PPA, reliability, and ... » read more

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
By Siemens EDA - 28 Jan, 2026 - Comments: 0

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high performance compute segemnts such as AI, Hyperscalers, Cloud datacenters, Neural processors and even autonomous vehicles. With the quantity of chiplets commonly exceeding double-digit numbers. Add to that the increasing usage of high-speed, low power and low latency high-bandwidth-memory ... » read more

Software-Defined Systems
By Ed Sperling - 26 Jan, 2026 - Comments: 0

Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

Balancing Training, Quantization, And Hardware Integration In NPUs
By Ann Mutschler - 26 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu... » read more

Addressing Critical Tradeoffs In NPU Design
By Ann Mutschler - 21 Jan, 2026 - Comments: 1

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven W... » read more

Blog Review: Jan. 21
By Jesse Allen - 21 Jan, 2026 - Comments: 0

Keysight's Armando Valim considers the impact of AI on the memory market as AI infrastructure pressure widens the gap between high-performance memory and lower-margin consumer memory and SSD, forcing manufacturers to make strategic decisions and define which markets to serve. Cadence's Reela Samuel breaks down the major 3D-IC packaging methods used today, from wafer stacking flows to hybrid ... » read more

Chip Industry Week in Review
By The SE Staff - 16 Jan, 2026 - Comments: 0

Geopolitics Taiwan and the U.S. signed a trade agreement this week, with TSMC and other Taiwanese companies collectively pledging to directly invest at least $250B in investments in advanced semiconductor, energy and AI production and capacity in the U.S.  The agreement also included Taiwan providing another $250B in credit guarantees for additional IC supply chain expansions in the U.S., cap... » read more

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