tag: Siemens EDA

The Race Begins For Much Bigger Abstractions In Data Centers
By Ed Sperling - 17 Feb, 2026 - Comments: 0

Key Takeaways Data center build-out is enabling much larger and more complex abstractions. Competition is building for digital/virtual twins across multiple industry segments, including automotive, aerospace, and chip manufacturing. AI, and particularly AI agents, will play a significant role in sorting through data to find potential trouble spots. The frenzy of new data cen... » read more

How Siemens Symphony Pro Enabled AnalogPort To Verify Complex Chip Interfaces
By Siemens EDA - 13 Feb, 2026 - Comments: 0

The semiconductor industry's shift toward chiplet-based architectures has created significant mixed-signal verification challenges for high-speed die-to-die interconnects. Traditional verification approaches force difficult trade-offs: Digital mixed-signal (DMS) flows sacrifice analog fidelity, while Analog mixed-signal (AMS) flows struggle with scalability and manual overhead. This paper detai... » read more

Formal Verification Fundamentals Remain Non-Negotiable In The New Verification Revolution
By Nicolae Tusinschi - 12 Feb, 2026 - Comments: 0

The semiconductor industry stands at a critical juncture. First-time silicon success rates have reached all-time lows, while design complexity continues to grow exponentially. System-on-chip designs now integrate billions of transistors, multiple processor cores, complex memory hierarchies, and sophisticated interconnect fabrics. In this environment, the stakes for verification accuracy have ne... » read more

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
By Ann Mutschler - 12 Feb, 2026 - Comments: 1

Key Takeaways • Chiplets and 3D-IC architectures add new thermal-mechanical stresses that can affect the reliability of entire systems. • As chiplets are assembled into packages, defectivity targets become more stringent for each component in a system. • Traditional silos are breaking down, forcing design teams to address issues such as materials choices that previously were handled by... » read more

UCIe’s Major Technical Components Are Now In Place
By Bryon Moyer - 12 Feb, 2026 - Comments: 0

Key Takeaways UCIe 3.0 doubles bandwidth and enhances manageability, addressing new use cases and following an annual update cycle since 2023. The growing demand for chiplet-based architectures in AI data centers is driven by the limitations of monolithic chips, making inter-chiplet communication and connectivity crucial. While UCIe was initially seen as feature-heavy, many of its ma... » read more

Are You Using Structural Patterns In An SLT Environment?
By Peter Orlando - 10 Feb, 2026 - Comments: 0

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be... » read more

Six 3D-IC Design Trends That Secure The AI Era
By Pratyush Kamal - 05 Feb, 2026 - Comments: 0

By Pratyush Kamal and Todd Burkholder Greater functionality, performance, and speed are in great demand in pervasive computing, RF, and automotive electronic systems, as well as most everything else. Complexity continues to skyrocket, leading many to say we are officially in the post-Moore’s Law world. In his seminal 1965 paper, “Cramming more components onto integrated circuits,�... » read more

Blog Review: Feb. 4
By Jesse Allen - 04 Feb, 2026 - Comments: 0

Siemens' Tova Levy examines thermal management in 3D-IC, including why heat behaves differently in vertical stacks and how to analyze and manage thermal risk earlier and more predictably to ensure a design can meet performance, reliability, and time-to-market targets. Cadence's Reela Samuel finds that known-good-die strategies, standardized die-to-die test access, and vertical reliability mo... » read more

Chiplet Fundamentals For Engineers: eBook
By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Opening The Door To STCO: Hierarchical Device Planning
By Todd Burkholder - 29 Jan, 2026 - Comments: 0

By Todd Burkholder and Per Viklund The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high-performance market segments, such as AI, hyperscalers, high-performance computing, cloud data centers, neural processors, and even autonomous vehicles. This increased design complexity has led to an explosion in device complexity and pin counts. It... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy