Blog Review: Feb. 4

Siemens’ Tova Levy examines thermal management in 3D-IC, including why heat behaves differently in vertical stacks and how to analyze and manage thermal risk earlier and more predictably to ensure a design can meet performance, reliability, and time-to-market targets.

Cadence’s Reela Samuel finds that known-good-die strategies, standardized die-to-die test access, and vertical reliability modeling are no longer optional optimizations but foundational requirements for scalable 3D-IC deployment.

Synopsys’ Greg Sorber highlights how system-level engineering is reshaping the way products are conceptualized, designed, and manufactured amid the push for increasingly intelligent vehicles and other physical AI products.

Lam Research’s Sam Sarkar shows how virtual fabrication can predict within-wafer variability problems before they occur on the fab floor, simulating thousands of scenarios to identify sensitive parameters, optimize recipes, and improve die yield without the time and cost of extensive wafer-based testing.

Arm’s Jason Zhu, Tyler Mullenbach, Damien Dooley, and Gian Marco Iodice explore how ExecuTorch and Arm Scalable Matrix Extension 2 are unlocking faster, more responsive on-device AI for mobile experiences like interactive image segmentation.

Keysight’s Anubhab Sahu warns that while Model Context Protocol improves the extensibility and composability of AI agents, the same flexibility also introduces a broad and largely underexplored attack surface.

Ansys’ Andrew Dimelow and Abdoul Niazi introduce a model-based approach that establishes a single design failure mode and effects analysis (DFMEA) solution inside system-oriented safety analysis software to support the architecture and requirements of multiple programs across OEMs and tier suppliers.

Swansea University’s Siraj Shaikh and SEMI’s Mayura Padmanabhan encourage participation in an effort that aims to strengthen cybersecurity across the semiconductor manufacturing ecosystem and develop evidence requirements that are suitable for broad adoption.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology editor Brian Bailey asks when verification is finished, and how much effort was wasted in getting to that point?

Keysight’s Niels Faché looks at the factors reshaping how teams work and the tools they use, including AI integration and chiplet ecosystem maturation.

Siemens EDA’s Todd Burkholder and Per Viklund dig into system technology co-optimization, advocating a process where IC partitioning information is forwarded to package prototyping at an early stage.

Arteris’ André Bonnardot brings together tightly coordinated data movement and low-latency on-chip storage for real-time environments.

Synopsys’ Krishna Balachandran explains how to build a layered defense model that ensures data remains protected even if physical access is gained.

Cadence’s Nayan Gaywala shows how to reduce energy and area costs while meeting performance requirements for RISC-V designs.