New Automotive Architectures Are Shaking Up Processor And Memory Choices


Key Takeaways Assisted and autonomous driving require more data from more sensors, and much faster processing of some of that data. The shift to software-defined vehicles and centralized intelligence makes it easier to identify where the most advanced processors and memories are required, and where older and less expensive technologies can be deployed. Technologies that were largely ... » read more

Blog Review: Mar. 4


Cadence's Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators. Siemens' Nicolae Tusinschi suggests that formal verification isn't just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware desi... » read more

Accelerate Your IP Selection With Smart Solido Library Profiler


This white paper discusses the IP selection process, its requirements, challenges, and proposed solutions. The process of choosing cell IP libraries for integrated circuit (IC) design is a slow and complicated process due to the inconsistencies and complexities of library files, particularly across sources, technology nodes, and variants. Manual methods to achieve IP selection not only consumes... » read more

Using Data And AI More Effectively In EDA


Key Takeaways The data being produced by EDA tools tends to be for human consumption and has weak semantics. Agents are attempting to create actionable information from unstructured data. The Model Context Protocol may provide AI with access to better data. Semiconductor design generates a lot of data, but how much of that is useful or currently being used by AI tools? And h... » read more

AI Starting To Simplify Design Of Programmable Logic


Key Takeaways AI/ML and agentic tools are getting better at helping design and compile FPGAs, but downstream programming is slower to benefit. FPGAs historically have been designed using Verilog or VHDL, but higher-level languages could push more intelligence into compilers. ML tools can also help with mixed-signal co-design by automatically tuning DSP algorithms based on analog simu... » read more

Verifying Scale-Up And Scale-Out In Data Centers


Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

Blog Review: Feb. 25


Cadence's Mick Posner introduces the Foundational Chiplet System Architecture, a specification that aims to deliver a vendor and CPU-neutral architecture, common system partition guidelines, and a shared vocabulary and set of standards for system-level and interface definitions between chiplets. Synopsys' Scott Knowlton explains why LPDDR6 represents a big step forward in memory management c... » read more

When Cleaning Chips Isn’t Clean Enough


Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures. For much... » read more

Blog Review: Feb. 18


Synopsys' Raja Tabet anticipates deployment of an agentic AI workforce within the next 12 to 24 months that can take on different engineering personas, such as a digital implementation agent, a verification agent, or an analog agent, to run experiments in parallel, generate and triage tests, and propose fixes. Cadence's Reela Samuel dives into power usage effectiveness in data centers and wh... » read more

Can A Computer Science Student Be Taught To Design Hardware?


Key Takeaways New approaches are being devised and tested to address the talent shortage. Leveraging AI in design tools will help engineers become more efficient, and potentially could reduce the time it takes to train engineering students. EDA companies are looking at whether it's possible to train computer science and software engineers to become hardware engineers. A vari... » read more

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