tag: Siemens EDA

AI Power on the Edge
By Brian Bailey - 12 Mar, 2026 - Comments: 0

Key takeaways Power and thermal become primary design considerations, not just optimizations. Hardware architectures need to be developed from the ground up. Hardware/software/model co-development is essential. Implementing AI on the edge is driven by a different set of metrics than training or even inference in the cloud. It makes power a first-class citizen, if not the mos... » read more

Scale Up, Scale Out Get a New Partner
By Bryon Moyer - 12 Mar, 2026 - Comments: 0

Key Takeaways: Three AI data center scaling strategies are scale-up, scale-out, and scale-across. Scale-up is within a rack; scale-out is between racks; scale-across is between data centers. Each of the three uses a different interconnect strategy to optimize either latency or jitter. As today’s data center workloads — especially for AI and HPC — outgrow the physical, ... » read more

Data-Driven Optimization In Semiconductor Manufacturing
By Ben Green - 11 Mar, 2026 - Comments: 0

Effectively scaling semiconductor manufacturing is critical to meeting the rapidly growing demand and requires solving numerous technical challenges. The substantial capital investment required for semiconductor manufacturing further complicates the business equation. Legacy fabs are designed redundantly to maintain the uptime required for reliable ROI, further increasing costs. Producers want ... » read more

Improving Yield Through Shared Data
By Ed Sperling - 11 Mar, 2026 - Comments: 0

Increasing complexity due to advanced packaging, multi-die assemblies, and more devices under test is having an impact on yield, which in turn slows time to market and impacts overall chip costs. What's needed is a way to share data that previously was siloed by chipmakers, fabs, and OSATs. Jayant D'Souza, technical product director at Siemens EDA, talks about the underlying drivers for sharing... » read more

Analog Scan: Unlocking A New Era In Mixed-Signal Test
By Vladimir Zivkovic - 10 Mar, 2026 - Comments: 0

Anyone involved in IC product sign-off that includes a mixed signal design portion knows that developing robust tests for these intricate designs has historically been a significant bottleneck, no matter the application. It's a hurdle many of us have faced, leading to extended development times, high costs, and sometimes an unsettling uncertainty about the true quality of our tests. Traditio... » read more

Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1

Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

The Future of Semiconductors: Engineering in the Convergence era
By Siemens EDA - 09 Mar, 2026 - Comments: 0

The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade. Moore’... » read more

Chip Industry Week In Review
By The SE Staff - 06 Mar, 2026 - Comments: 0

Think tank IAPS' report on AI integrity attacks contends that advanced AI systems must be protected from hidden tampering, backdoors, or unauthorized changes that could alter their behavior or outputs, especially when AI adoption is scaling rapidly, with over 60% of the federal workforce now using AI every day. Geopolitics The U.S. government has drafted new export rules that may give W... » read more

Across The Vast Reaches Of The 3D Stack: Mastering ESD Verification In Advanced Semiconductor Design
By Keerthana Chelur Hithesh - 05 Mar, 2026 - Comments: 0

Introduction: The epic challenge In the vast reaches of the semiconductor cosmos, a silent menace lurks—one that can obliterate years of design work in a fraction of a nanosecond. Electrostatic discharge (ESD) verification stands as the guardian against this invisible threat, a critical discipline that separates the triumphant chip designs from the smoldering wreckage of failed silicon dream... » read more

Auto Security Accelerates With Standardization And Certified Silicon
By Ann Mutschler - 05 Mar, 2026 - Comments: 0

Key Takeaways The automotive sector is actively developing and delivering secure parts and features ranging from secure boot to encrypted data and in-network protections. The cost of a breach can involve everything from ransomware to liability and/or damage to a brand. New standards are being introduced to ensure security, and technology developers are integrating cybersecurity requi... » read more

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