IC Security Threats Spike With Quantum, AI, And Automotive


Key Takeaways: The top challenge for the chip architect is building post‑quantum cryptography securely into real hardware from the start, not just selecting approved algorithms. Security must be treated as a core silicon architecture decision early on, especially for long‑lived, automotive, and multi‑vendor systems. Automotive cybersecurity now requires a holistic approach span... » read more

Blog Review: April 1


Siemens EDA's Harry Foster considers why first-silicon success is continuing to decline even though tools are capable of handling much larger design sizes and identifies how increasingly complex interactions between components cause traditional verification assumptions to break down. Synopsys' Eldo N Baby explores dynamic voltage drop analysis, including how to bring in switching scenario in... » read more

Detect, Diagnose, And Debug Using Sensors And Functional Monitoring


By Hari Mani, Henrique Mendes, and Robert Wilcox Modern AI workloads drive an extremely "spiky" power profile where current demands surge to hundreds of Amps within nanoseconds, clashing with the tighter operating ranges of advanced process nodes as they push below 0.8V. This creates a physical bottleneck: the on-die power delivery network (PDN) cannot sustain the instantaneous curren... » read more

Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails


By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is near... » read more

Chip Industry Week In Review


War impacts The Iran War's toll on the chip industry is widening. Over 95% of Taiwan's energy is imported, causing the country to secure alternative sources. Korea is also heavily dependent on energy imports from the Middle East. Shortages of key materials are cropping up everywhere. Helium from Qatar, the second largest producer behind the U.S., is constrained by hostilities in the Per... » read more

Liquid Cooling Drives Other Localized Cooling


Key Takeaways: When converting from air to liquid cooling, components without liquid may become too hot. An entire board or system must undergo thermal analysis to ensure that any components that were once cool enough remain cool. Alternative cooling techniques may be needed for components without liquid cooling. Liquid cooling is proving effective at cooling high-power chip... » read more

Human-Centered Agentic AI Workflows For RTL Verification


Productivity challenges in modern semiconductor development stem less from individual tool limitations and more from process-level complexity across design creation, verification, and iteration. Agentic EDA addresses this shift by embedding intelligence directly into workflows that span creation and validation. The Questa One Agentic Toolkit extends the Questa One solution with human-centere... » read more

AI Design Reshapes Data Management


Key takeaways: Integrating AI into chip workflows is pushing companies to overhaul their data management strategies, shifting from passive storage to active, structured, and machine-readable systems. As training and inference workloads grow, data movement, congestion, and energy efficiency become the dominant challenges, often surpassing raw compute capability. Proprietary and comple... » read more

Human-Centered Agentic AI Comes To RTL Verification


For decades, productivity gains in electronic design automation (EDA) came from better engines. Faster solvers, higher-capacity simulators, and more scalable formal tools allowed design and verification teams to keep pace as designs grew larger. That model is no longer sufficient. Today’s design and verification bottleneck is not raw tool performance, but the coordination overhead required... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers


Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

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