Robust extraction empowers semiconductor innovation at the most complex nodes.
By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala
In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is nearly exhausted. To move forward, they must stack transistors vertically and power them from within the silicon itself. The boldest experiments in this new “vertical city” are complementary field-effect transistors (CFETs) and buried power rails (BPRs)—a paradigm shift in both design strategy and engineering execution.
This increase in device complexity requires precise extraction of parasitic resistance and capacitance to ensure reliability and performance. Fortunately, tools are available that support extraction for both front and back metal stacks, including interfaces, through silicon vias (TSVs) and non-Manhattan routing.
At process nodes below 5 nm, the physics of scaling confront engineers with a wall of complexity. Not long ago, the shift from planar to finFETs signaled a leap in electrostatic control and density, but as foundries race toward 3nm and smaller, traditional solutions are not enough. More transistors must fit into the same space without sacrificing speed, power or reliability. The answer is architectural, not incremental.
CFETs reimagine the basic field-effect transistor by vertically stacking n-type and p-type transistors—akin to constructing two skyscrapers on the same footprint but on different levels (Figure 1).
Fig. 1: An example of a CFET inverter circuit from Intel, unveiled at IEEE International Electron Devices Meeting (IEDM) in 2020. It stacks NFET and PFET transistors one atop the other.
This approach doubles device density without requiring new horizontal real estate. But density alone is not the answer; powered skyscrapers need power lines that don’t clog the streets. That’s where buried power rails come in. By routing power supplies beneath the transistor layer—essentially building a subway for electric current—designers free up precious metal layers for signal routing and minimize voltage drop.
However, new heights and depths bring new invisible risks. Parasitic resistances and capacitances become multi-dimensional, emerging from the interfaces between stacked transistors, complex contact geometries and the interaction between frontside and backside routes. The elegant symmetry of a schematic gives way to electromagnetic fields and the subtle interplay of materials. The challenge isn’t simply designing CFETs and BPRs—it’s extracting and modeling every parasitic effect that could threaten the device’s integrity under real-world signals and power loads.
Just as engineers had to invent new building codes, seismic analyses and inspection methods for New York’s vertical ambitions, chip designers now need novel tools and workflows to ensure that every hidden resistor, capacitor and coupling path is identified, quantified and managed from the earliest design stages.
Extraction, in advanced nodes, is no longer a matter of running a well-worn script at signoff. For CFET and BPR-enabled designs, it means orchestrating physics-aware models that capture everything from TSVs and non-Manhattan routing to hybrid stacks of heterogeneous materials. The “old rules” of RC extraction do not account for current flowing through the back of the wafer, for the vertical interfaces between stacked channels, or the minute, complex 3D geometries that define coupling.
Consider Figure 2, which shows the intricate mesh of frontside and backside metal layers, with buried power rails threading beneath active device layers and feeding both nFET and pFET transistors. Each interface, each crossing and each vertical interconnect introduces resistance and inductance that must be properly captured before a designer can trust simulated IR drop and signal behavior.
Fig. 2: Power distribution networks with buried power rails.
Capacitance modeling is equally daunting. At 3nm and beyond, coupling is not confined to adjacent wires but includes field interactions across multiple layers—affected by the relative position of BPRs, the proximity of TSVs and the fine detail of the local geometry. Even small changes in the dielectric patterning or the exact layout of the rails may introduce enough parasitic capacitance to tip a path from reliable to failure-prone.
To tame these complexities, extraction tools must address three essential dimensions:
The Siemens approach, exemplified by Calibre xACT, is to unify these requirements into a single extraction environment. Rather than fragmenting the problem into frontside and backside stages, Calibre xACT applies technology files that include both traditional and new BPR/CFET-specific rules and produces netlists and parasitics that preserve the fidelity required for electrical verification, timing and reliability simulation.
The difference is more than technological; it is foundational. Without holistic extraction, even the most innovative CFET+BPR designs risk early failure or silicon surprises—analogous to discovering, during the first subway’s construction, that your skyscraper’s foundation cannot bear the load. Only a workflow that unifies extraction, analysis and rule integration can capture these subtle but critical interactions—and empower engineers to manage risk before tapeout.
Working at the edge of technology means workflows must adapt—not simply speed up. The extraction process for CFET and buried power rail designs follows a concise yet rigorous series of steps, each demanding discipline and precision.
The process starts with geometry preparation. Designers import the layout database, ensuring full representation of the multi-level stack, including both standard cell geometries and custom BPR placements. Next, extraction rules are built or extended. These rule decks specify the electrical properties—such as sheet resistance, interface resistance and dielectric constants—unique to every relevant layer. In the CFET+BPR regime, this frequently means collaborating with process engineers to verify foundry-supplied data and running test structures to validate electromagnetic solver results.
At this stage, integrating RLCK modeling becomes vital. Designers must simulate not just resistance and capacitance, but also inductance (from long vertical or diagonal runs) and coupling effects, which are pronounced at these extreme scales.
Once the rule decks and technology files are validated, the extraction engine is run—often iteratively, as results are checked against reference structures, signoff requirements and circuit simulations. Each iteration may reveal unanticipated parasitic loops or underestimated coupling, particularly around TSVs or in areas where the physical implementation diverges from the design abstraction.
The next step is parasitic netlist generation. Here, Calibre xACT produces a detailed, simulation-ready netlist that retains all relevant parasitics from both the frontside and backside metal stacks. This netlist feeds directly into static timing analysis, signal integrity and power analysis tools.
Throughout, the workflow supports close debug and refinement loops. Engineers can visualize extracted values directly against layout cross-sections, drill down into specific nets or interface points (see relevant cross-sectional and layout images in the paper) and trace sources of IR drop or noise. The accuracy of this stage is what ultimately gives design teams the confidence that their innovation will stand up to the brutal realities of silicon.
Perhaps most importantly, this unified approach reduces the likelihood of late-stage surprises—cause for costly respins or, worse, failed products. A design built on sand may rise quickly, but only one built on solid, well-extracted ground stands tall in the long run.
The history of technology is a story of ambition: to build higher, denser and more efficiently than before. But the lesson from city builders—whether in Manhattan or in the nanoscopic cities etched onto a silicon wafer—is that new horizons demand new infrastructure, new codes and new tools.
CFETs and buried power rails embody the future of semiconductor scaling, offering paths to performance and efficiency that just a few years ago seemed unreachable. But these breakthroughs mean little without rock-solid confidence in the way every hidden interaction is captured, modeled and verified. The intricacies of CFET+BPR integration demand a new generation of extraction workflows, ones that can traverse the full “depths and heights” of the chip and surface actionable information for every possible design and process variation.
Through robust, physics-based extraction as enabled by Siemens Calibre xACT, IC designers gain the certainty they need to move boldly into uncharted territory—to build the skyscrapers and subways of tomorrow’s silicon. In this new era, innovation is not just what you see on the skyline of a device outline, but what lies underneath: the invisible, meticulously modeled networks that make modern chips possible.
For details, download our full technical paper: Extraction challenges of CFET and backside power delivery.
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