Blog Review: Jan. 7


Cadence's Reela Samuel presents an overview of through-silicon vias, including structure, pitch, and electrical behavior, key layout rules such as keep-out zones and stress constraints, and how TSV parasitics influence bandwidth, latency, and system-level performance. Siemens' Andras Vass-Varnai identifies five thermal trends to watch and how they’ll reshape design and packaging workflows ... » read more

Blog Review: Dec. 24


Cadence's Jakob Engblom shares highlights from the recent SDV Europe conference, including why software-defined vehicles will require much closer, faster collaboration between suppliers and customers, with virtualization for software development and testing taking on a key role, as well as API questions and tire sensors. Synopsys' Tom De Schutter and Marc Serughetti predict that new cars wil... » read more

When To Move To Multi-Die Assemblies


As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

The Power Of Shift-Left DRC Verification With Calibre nmDRC Recon


As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design


As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts. Foundry rules, shrinking geometries and advanced patterning have increased both the engineering effort and computational overhead needed for verification. Today, DRC isn’t just about sign-off—it�... » read more

Chip Industry Week in Review


Government funding/defunding NIST is terminating funding for the SMART USA Institute, a CHIPS Act research center focused on digital twins, prompting congressional concern that the decision disrupts active awards and weakens U.S. semiconductor R&D commitments. Korea Zinc was awarded $210M in CHIPS Act funding towards a new $6.6B Tennessee advanced smelter and minerals processing facility,... » read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a... » read more

Blog Review: Dec. 17


Cadence's Shyam Sharma checks out what's new in the latest Open NAND Flash Interface 5.2 standard, including a Separate Command Address protocol that allows Hosts to optimize the command and data scheduling to increase overall available bandwidth. Siemens' Kyle Fraunfelter and Melville Bryant contend that improving semiconductor manufacturing and fab sustainability starts with a digital twin... » read more

Environmental Sensors Catch More Data For A Greener World


Sensors to detect temperature, pressure, and gases, such as CO2, have been around for centuries. However, the latest devices can measure a growing list of substances and process the data in real-time. Likewise, single-use sensors to measure pH levels in water are well established, but the latest water sensors can be deployed all along the pipeline from source to processing to outlet or tap, sav... » read more

AI Buildout Makes HPC Simulation More Challenging


Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

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