As modern system design brings together components that were once isolated, abstractions are breaking down.
Over the past several decades studying verification practices across the semiconductor industry, I’ve watched assumptions that once held up remarkably well begin to strain under the weight of modern system complexity. This is not a loss of engineering rigor. It is the result of systems that no longer conform to the boundaries earlier design models depended on.
For much of the industry’s history, semiconductor design progressed under a powerful simplifying assumption: that complex problems could be separated into largely independent domains. Logic, timing, power, thermals, software, and packaging could be optimized in isolation. This orthogonalization enabled specialization, predictable design flows, and decades of scaling progress.
That assumption is now failing.
As many designs move beyond monolithic silicon into heterogeneous, multi-die, software-defined platforms operating under tight physical constraints, the separation of concerns that once anchored design and verification is eroding and, in many cases, collapsing entirely. This shift is forcing verification to evolve from a pre-silicon phase into a continuous, lifecycle discipline.
The effects of this transition are most visible in verification.
Orthogonalization was never merely an organizational convenience. It was an implicit engineering contract that allowed teams to reason about correctness within bounded domains.
At the chip level, much of this contract still holds, though less reliably than before. RTL functionality, timing closure, power analysis, and software validation still can be addressed independently. But the seams between them are coming apart. Power states influence functional behavior. Thermal gradients affect timing correctness. Mixed-signal blocks blur digital and analog boundaries. Software workloads reshape memory and coherency behavior.
Orthogonalization within the chip has weakened, but it has not disappeared.
Above the chip level, however, it has largely collapsed.
Modern systems are defined by integration. Chiplets, advanced packaging, and 3D IC technologies tie together components that were once isolated, sometimes sourced from different vendors and designed under different assumptions.
Hybrid bonding improves bandwidth but alters timing. Thermal drift changes latency and coherency relationships. Photonic interconnects introduce bandwidth that varies with temperature. Cross-die fabrics reshape ordering and performance under load. And, in stacked designs, mechanical stress and warpage become functional variables, not just reliability concerns.
At the same time, software has become a dominant determinant of hardware behavior. Firmware updates, orchestration layers, and AI model deployments continuously reshape workloads in the field. Those workloads, in turn, influence power density, temperature distribution, and performance characteristics.
These behaviors do not belong cleanly to any single domain. They emerge from interactions across silicon, packaging, physics, and software.
This is not simply increased complexity. It is the breakdown of abstraction.
When orthogonalization holds, failures tend to be local and diagnosable. When it fails, failures become emergent.
What has stood out most clearly in recent industry studies is not insufficient verification effort, but a growing mismatch between verification assumptions and system reality. Issues increasingly surface only under specific combinations of workload, thermal state, power mode, and software version. In practice, this may look like a coherency failure that appears only under sustained AI workloads at elevated temperatures, or a post-deployment firmware update that quietly destabilizes power integrity margins.
These failures may evade pre-silicon validation and emerge months after deployment. Root-cause analysis becomes difficult because no single layer is solely responsible.
In this environment, verification becomes the point where reality asserts itself.
Traditional verification—simulation, emulation, formal analysis, and signoff rigor—remains essential. These techniques establish a baseline of trust. But they rely on assumptions that do not remain valid once systems are deployed.
Correctness is no longer a static property established before tapeout. It evolves with system use.
For much of the industry’s history, verification followed a predictable arc: define intent, verify implementation, tape out, ship. Once silicon left the fab, verification was largely considered complete.
That model no longer reflects reality.
As a system remains in service, the conditions that define correct behavior continue to shift. Workloads evolve, attack surfaces expand, and power and thermal envelopes are pushed in ways that were difficult to anticipate during design. These changes steadily erode the assumptions that defined correctness at tapeout.
Each shift effectively creates a new verification event long after silicon has shipped.
Traditional IC verification remains essential, but it establishes correctness at a point in time. Modern systems require correctness to be maintained over time.
For an increasing class of complex, software-defined systems, traditional verification plus lifecycle verification is becoming the new reality.
For verification teams, this means correctness must be defended long after tapeout. For system architects, it means abstraction boundaries can no longer be assumed to hold once systems are deployed at scale.
Lifecycle verification works only if design-time assumptions can be reconciled with behavior observed in deployment. In practice, this requires a persistent system model that evolves alongside the product.
Today, teams often rely on disconnected logs, postmortems, and ad-hoc debug when failures emerge in the field. Lifecycle verification instead demands continuity of intent, assumptions, and models from design through deployment and operation.
This is not a single, monolithic representation. It is a hybrid, cross-domain model that connects functional behavior, workload characteristics, and physical effects across the system’s lifetime.
Without such a model, lifecycle verification degrades into disconnected snapshots: pre-silicon assumptions on one side, in-field failures on the other, with no coherent way to relate them.
No single verification engine can capture system-level truth. Simulation provides accuracy but limited scale. Emulation enables realistic workloads but abstracts physics. Prototyping accelerates software development but sacrifices observability. Physical solvers model thermals, stress, and electrical behavior but lack functional context.
Lifecycle verification depends on coordinating these views, not replacing them.
Even if hardware integration complexity stabilized, software-defined behavior ensures that lifecycle verification is unavoidable.
Modern products are designed to change after deployment. Firmware updates, configuration changes, and evolving workloads are expected. Hardware and software now co-evolve, and verification must track that moving boundary.
This is especially evident in domain-specific architectures. As general-purpose scaling plateaus, specialized accelerators proliferate, optimized for particular data types, execution models, and workloads. Their behavior cannot be validated independently of software intent.
In such systems, correctness is inseparable from use.
As verification expands across domains and across the product lifecycle, a new bottleneck emerges: orchestration.
Coordinating simulation, emulation, prototyping, physical analysis, and regression while adapting to changing workloads and updates quickly exceeds what manual workflows can sustain. The challenge is no longer the availability of verification engines, but the ability to deploy them coherently and repeatedly as systems evolve.
Maintaining a consistent system-level view becomes less about maximum fidelity at a single moment and more about continuity across changing conditions. Verification intent must persist as workloads shift, software changes, and operating envelopes evolve.
This is where a new class of automation is emerging. Rather than treating AI as a feature inside individual tools, teams are beginning to apply agentic AI at the workflow level. The goal is not to replace engineering judgment, but to manage coordination across increasingly complex verification flows.
Early forms of this approach are already appearing in large-scale verification environments, driven less by novelty than by the practical need to manage scale and complexity.
In practice, this means using AI to interpret verification intent, plan and schedule the appropriate mix of engines, manage iteration depth, analyze results, and adapt verification strategies as systems change. Engineers define goals and constraints. The orchestration adapts accordingly.
Agentic AI is emerging not as a new verification methodology, but as a response to the orchestration demands created by lifecycle verification itself.
The semiconductor industry is entering a convergence era in which silicon, software, physics, packaging, security, and power constraints are tightly intertwined. Device scaling still matters, but it no longer defines the trajectory of progress.
Architecture, integration, verification, and automation do.
The end of orthogonalization is not a failure of engineering discipline. It is the natural consequence of systems that are more integrated, adaptive, and physically constrained than those of the past.
The teams that succeed will be those that combine powerful verification engines with the ability to sustain verification intent as systems evolve.
Success will not come from restoring old boundaries. It will come from accepting their absence and building verification strategies that span domains, persist across lifecycles, and evolve alongside the systems they protect.
Verification is no longer a phase. It is a discipline that lasts as long as the product itself.
To read more on the real breakthroughs that will come from system-level engineering—from the way we assemble, integrate, and optimize entire platforms—please read Harry’s new paper, The Future of Semiconductors: Engineering in the Convergence Era.
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