tag: Siemens EDA

Interoperability And Automation Yield A Scalable And Efficient Safety Workflow
By Ann Keffer - 07 Mar, 2024 - Comments: 0

By Ann Keffer, Arun Gogineni, and James Kim Cars deploying ADAS and AV features rely on complex digital and analog systems to perform critical real-time applications. The large number of faults that need to be tested in these modern automotive designs make performing safety verification using a single technology impractical. Yet, developing an optimized safety methodology with specific f... » read more

V2X Path To Deployment Still Murky
By Ann Mutschler - 07 Mar, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss Vehicle-To-Everything (V2X) technology and the path to deployment, with Shawn Carpenter, program director for 5G and space at Ansys; Lang Lin, principal product manager at Ansys; Daniel Dalpiaz, senior manager product marketing, Americas, green industrial power division at Infineon; David Fritz, vice president of virtual and hy... » read more

Complex Safety Mechanisms Require Interoperability And Automation For Validation And Metric Closure
By Siemens EDA - 06 Mar, 2024 - Comments: 0

The race to autonomous mobility among the automobile manufacturers is driving the evolution of the underlying semiconductors. As a result, semiconductor technologies are moving towards higher densities and lower operating voltages, and this migration is introducing increasing sensitivity to random hardware failures – the failures which occur unpredictably over a semiconductor’s lifetime. Mo... » read more

Chiplet IP Standards Are Just The Beginning
By Ann Mutschler - 06 Mar, 2024 - Comments: 2

Experts at the Table: Semiconductor Engineering sat down to talk about chiplet standards, interoperability, and the need for highly customized AI chiplets, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen S... » read more

Blog Review: Mar. 6
By Jesse Allen - 06 Mar, 2024 - Comments: 0

Synopsys' Gandharv Bhatara notes that successfully deploying high-NA EUV will rely on computational lithography to provide accurate modeling of aberrations, compact 3D mask modeling, and expand inverse lithography to full-chip processing. Cadence's John Park argues for using a systematic and automated system for co-design and co-analysis of multi-die packages to reduce the margin for human e... » read more

Optimizing EDA Cloud Hardware And Workloads
By Aharon Etengoff - 04 Mar, 2024 - Comments: 0

Optimizing EDA hardware for the cloud can shorten the time required for large and complex simulations, but not all workloads will benefit equally, and much more can be done to improve those that can. Tens of thousands of GPUs and specialized accelerators, all working in parallel, add significant and elastic compute horsepower for complex designs. That allows design teams to explore various a... » read more

Commercial Chiplet Ecosystem May Be A Decade Away
By Ann Mutschler - 29 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the challenges of establishing a commercial chiplet ecosystem with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA product mana... » read more

Maximizing Efficiency And Productivity: The Benefits Of Shift Left Verification For IP Designers
By Terry Meeks - 29 Feb, 2024 - Comments: 0

Intellectual property (IP) designers play a crucial role by creating reusable components that form the building blocks of larger integrated circuit (IC) designs. These components, whether developed in-house or acquired from specialized IP design companies, are essential for providing core functionality such as memory and standard libraries. However, designing and verifying IP is a complex and d... » read more

A Game-Changer For IP Designers: Design-Stage Verification
By Siemens EDA - 28 Feb, 2024 - Comments: 0

Discover how to transform your IP design process with the Calibre Shift left initiative. In this new technical paper, you’ll gain valuable insights into how, by moving physical verification earlier in the IP design flow, you can locate and correct design errors sooner, reducing costs and getting complex designs to market faster. Dive into the challenges of hard, soft and custom IP creation, a... » read more

Blog Review: Feb. 21
By Jesse Allen - 21 Feb, 2024 - Comments: 0

Siemens' John McMillan digs into physical verification maturity for high-density advanced packaging (HDAP) designs and major differences in the LVS verification flow compared to the well-established process for SoCs. Synopsys' Varun Shah identifies why a cloud adoption framework is key to getting the most out of deploying EDA tools in the cloud, including by ensuring that different types of ... » read more

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