How Fast Can Germany Shift To Software-Defined Vehicles?


It's being called "China speed," defined by the accelerated rate at which software-defined vehicles can be designed, manufactured, and updated with new features. And nowhere is this hitting harder and forcing more profound changes than in Germany, Europe's leading automotive market. Rather than relying solely on customized electronic control units, SDVs use a combination of specialized and g... » read more

Combining SPICE With IBIS-AMI: Solving Advanced Signal Integrity Verification Challenges With Solido SPICE


This paper explores current technology trends in high-speed links, including high-speed memory and SerDes applications, highlighting the critical roles of combined SPICE-level and IBIS-AMI modeling for accurate verification. Verifying high-speed links with IBIS-AMI during the circuit design phase presents significant complexity due to the combined effects of equalization schemes, channel S-para... » read more

Formal Verification’s Value Grows


Experts at the table: Semiconductor Engineering sat down to discuss why formal verification is becoming more important, with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA. Wha... » read more

Blog Review: Nov. 5


Synopsys' Igor Markov points out how numerical simulation tools advance quantum computing R&D by capturing both quantum-mechanical behavior and classical electromagnetic effects so researchers can evaluate design alternatives before fabrication and gain insight into how devices operate under realistic conditions. Siemens' Stephen V. Chavez finds that impedance modeling and control are mi... » read more

The Next Big Thing


Sometimes, we spend so much time looking for the next big thing that we actually miss something even bigger. I have to admit I was guilty of this while employed by a large EDA company 20 years ago. I was one of those ESL people — Electronic System Level acolytes, with Gary Smith as our standard bearer. We wanted to do many things, including raising the level of abstraction for design and veri... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops


As system-on-chip (SoC) designs evolve, they aren’t just getting bigger — they’re becoming more intricate. One of the trickiest challenges in this evolution lies in handling resets. Today’s architectures often juggle multiple asynchronous reset sources alongside sequential elements such as non-resettable registers (NRRs), which operate without dedicated reset pins. When a signal crosses... » read more

Thermal, Mechanical, And Material Stresses Grow With Die Stacking


Managing thermal and mechanical stress in multi-die assemblies will require a detailed knowledge of how and where a device will be used, how it will be packaged, and where stresses could cause problems at any point during its expected lifetime. This includes everything from workload-dependent thermal gradients to mechanical and electrical stress, which may become more pronounced over time wi... » read more

Even With AI Inroads, Human Chip Designers Still Essential


The proliferation of AI tools seems perfectly matched to fill a talent shortage, but a closer look shows the skills do not entirely overlap. Certain parts of the EDA pipeline require human engineers, and it seems likely to stay that way for the foreseeable future. The dark art of analog design, the final word on safety-critical functional safety, high-level architectural decisions, product i... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops


The importance of reset domain crossing (RDC) verification in ensuring robust and reliable SoC operation cannot be overstated. Verification tools for RDCs are essential in identifying potential metastability issues and ensuring that signal transitions across reset domains are properly handled. This paper presents a novel approach to tackling the challenges of RDC verification involving non-rese... » read more

Blog Review: Oct. 29


Siemens' Ujjwal Negi and Prashant Dixit warn that while UCIe 3.0 improves performance and efficiency through higher data rates, runtime recalibration, priority sideband messaging, low-power sideband operation, and circular buffer transport, those enhancements also increase verification complexity. Cadence's Anika Sunda suggests that a unified digital thread that connects verification environ... » read more

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