tag: Siemens EDA

Noise: A Chip Killer
By Brian Bailey - 13 Nov, 2025 - Comments: 0

Noise has always been important to communications experts, but it's quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised. Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intende... » read more

Power Integrity And Voltage Issues Get Harder To Detect And Solve
By Ann Mutschler - 13 Nov, 2025 - Comments: 0

Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis
By Farhad Ahmed - 13 Nov, 2025 - Comments: 0

The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Standardization Of HDMs For Hierarchical CDC And RDC Analysis
By Siemens EDA - 12 Nov, 2025 - Comments: 0

Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the s... » read more

Keeping The Lights On: How Digital Twins And Smart Semiconductor Management Power Our 24/7 World
By Lee Harrison - 11 Nov, 2025 - Comments: 0

Hey there, tech enthusiasts and digital pioneers! Have you ever stopped to think about the tiny, intricate components that keep our modern world humming? From the advanced safety features in your car to the massive data centers powering AI, semiconductors are truly the unsung heroes. But what happens when these tiny titans face immense pressure, like the non-stop demands of AI workloads? That's... » read more

AI In Test Analytics: Promise Vs. Reality
By Gregory Haley - 11 Nov, 2025 - Comments: 0

The semiconductor industry is increasingly turning to artificial intelligence as the solution for increasing complexity in test analytics, hoping algorithms can tame the growing flood of production data. The need to extract actionable insight from that torrent is pressing. AI/ML (AI) models promise to find correlations buried in multidimensional datasets, predict failures before they occur, and... » read more

New Rules Put The Squeeze On Semiconductor Gray Market
By Anne Meixner - 11 Nov, 2025 - Comments: 0

The shift toward chiplets and multi-die assemblies is forcing big changes in the global supply chain, including much tighter cooperation between companies and governments to ensure the authenticity and quality of semiconductor parts. The chip industry has been looking to digital certificates as the best means of reducing counterfeiting and ensuring consistent quality for some time. The probl... » read more

Integrating Design Verification To Approach Zero Defects
By Jyothy Jaganathan - 06 Nov, 2025 - Comments: 0

As semiconductor applications in automotive, data center, and high-performance computing grow increasingly mission-critical, the industry faces mounting pressure to achieve near-perfect manufacturing test coverage—often exceeding 99%. Yet, meeting stringent zero-defect defective parts per million (DPPM) targets remains a formidable challenge. Traditional structural testing methods frequently ... » read more

Moving AI Workloads To The Edge
By Ann Mutschler - 06 Nov, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss how some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president an... » read more

How Fast Can Germany Shift To Software-Defined Vehicles?
By Emma Riverso - 06 Nov, 2025 - Comments: 0

It's being called "China speed," defined by the accelerated rate at which software-defined vehicles can be designed, manufactured, and updated with new features. And nowhere is this hitting harder and forcing more profound changes than in Germany, Europe's leading automotive market. Rather than relying solely on customized electronic control units, SDVs use a combination of specialized and g... » read more

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