tag: Siemens EDA

Optimizing AI Workloads For Edge Computing
By Ann Mutschler - 03 Dec, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss how some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president an... » read more

3DKs: Making Headway On Chiplet Standards
By Laura Peters - 01 Dec, 2025 - Comments: 0

The chiplet model has been proven by the early adopters. Large companies that successfully developed chips at leading nodes have integrated multiple chiplets into systems, where the entire silicon cycle is performed in-house. But the industry’s long-term goal of a free and open chiplet marketplace, in which companies of any size can reap the rewards and economies of scale associated with mult... » read more

Blog Review: Nov. 26
By Jesse Allen - 26 Nov, 2025 - Comments: 0

Cadence's Rajneesh Chauhan explains CXL's low power state, L0p, which maintains partial lane activity for efficient power management without compromising performance, and how comprehensive verification can help ensure reliable implementation. Siemens' John Ferguson provides a brief history of design rule checking, major advancements over the years, and why introducing it in earlier design st... » read more

AI Plays Multiple Roles Within EDA
By Brian Bailey - 25 Nov, 2025 - Comments: 0

AI's infusion into our world may seem sudden and unexpected, but EDA has been quietly adopting it for more than a decade. What's changed is that it's now becoming more visible, thanks to increasingly powerful large language models (LLMs) and the need to apply them to increasingly challenging multi-physics problems. Two fundamental shifts underlie AI's increasing prominence. First, heat is be... » read more

Securing IP Integrity In Advanced SoC Design
By Sara Khalaf - 25 Nov, 2025 - Comments: 0

In today’s complex system-on-chip (SoC) design flows, intellectual property (IP) blocks are everywhere—licensed from third parties, leveraged from internal libraries, or hand-crafted by expert teams. These IPs are typically delivered in a “black box” format and are expected to remain unchanged throughout the physical design stages, from initial floorplanning to top-level placement, rout... » read more

The Real-World Impact Of Silicon Lifecycle Management On Chip Architectures
By Ann Mutschler - 25 Nov, 2025 - Comments: 0

Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, under... » read more

Guarantee IP Integrity With Calibre IP Checker
By Siemens EDA - 25 Nov, 2025 - Comments: 0

In complex SoC designs, intellectual property (IP) blocks are critical yet vulnerable. Unintended modifications to IP during placement, routing or fill stages often go undetected by traditional DRC, leading to functional failures, performance degradation and costly re-spins. This paper introduces Calibre IP Checker, an automated, shift-left solution designed to guarantee IP integrity. It works ... » read more

Chip Industry Week In Review
By The SE Staff - 21 Nov, 2025 - Comments: 0

China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Blog Review: Nov. 19
By Jesse Allen - 19 Nov, 2025 - Comments: 0

Cadence's Mamta Rana explores how Forward Error Correction in PCIe 6.0 is key to its 64.0 GT/s per lane bandwidth by enabling the receiver to detect and correct errors without retransmissions or protocol-level recovery by adding redundant information to transmitted data. Siemens' Dave Rich shares a paper from DVCon 1992 that introduced a new RTL modeling construct to Verilog, eventually know... » read more

Edge AI Is Starting To Transform Industrial IoT
By Liz Allan - 17 Nov, 2025 - Comments: 0

A slew of wireless and increasingly multi-modal sensors is being targeted at the Industrial Internet of Things (IIoT), setting the stage for significant improvements in efficiency, higher yield, and reduced downtime. Wired IIoT devices, such as smart energy meters and breakers, industrial network gateways, and environmental sensors already are well established in factory settings. They have ... » read more

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