Blog Review: Nov. 26

Cadence’s Rajneesh Chauhan explains CXL’s low power state, L0p, which maintains partial lane activity for efficient power management without compromising performance, and how comprehensive verification can help ensure reliable implementation.

Siemens’ John Ferguson provides a brief history of design rule checking, major advancements over the years, and why introducing it in earlier design stages can avoid costly surprises later.

Synopsys’ Frank Schirrmeister, Rita Horner, and Todd Koelling share ten tips for achieving first-pass silicon success when developing AI chips, from prioritizing early architecture exploration to implementing test and lifecycle management capabilities.

Arm’s Volodymyr Turanskyy highlights updates in LLVM 21 that provide various performance and code generation improvements, including unrolling search loops, register pressure estimation, a set of whole-tensor operations, and elimination of unnecessary BTI instructions.

Keysight’s Hwee Yng Yeo suggests that the combination of 6G and AI could open up new opportunities in key industries such as automotive, manufacturing, defense, consumer electronics, and gaming.

Ansys’ Caty Fairclough checks out how a company operating satellite constellations uses digital mission engineering software to help monitor the environment, provide connectivity in remote or low-infrastructure areas, and maintain communication pathways during natural disasters.

SEMI’s Krish Dharma and Beebolt’s Talal Abu-Issa argue that the old “just-in-time, globally concentrated” supply chain model can no longer carry the industry forward as it faces a convergence of pressures from geopolitical tensions and climate risks to accelerating innovation cycles.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials and Systems & Design newsletters:

Technology editor Brian Bailey suggests how tools could take power seriously, given its importance to many chip designs.

Lam Research’s Assawer Soussou points to the benefits of virtual fabrication in assessing edge placement error and for successfully patterning 18nm metal pitches.

yieldWerx’s Aftkhar Aslam shows how to identify the source of problems in heterogeneous integration.

Amkor’s Vineet Pancholi discusses how evolving standards, design-for-test strategies, and automation can benefit multi-die assemblies.

Synopsys’ Shela Aboud explains why power, performance, and area metrics are no longer sufficient to capture the full range of design goals.

Microtronic’s Errol Akomer digs into how wafer manufacturers can address the talent shortage through better wafer inspection.

SEMI’s Clark Tseng and Nishita Rao offer approaches for uncertain tariff and trade policies.

Baya Systems’ Nandan Nayampally explains why modern AI systems require dynamic, adaptable software layers built to handle changing computational needs.

Siemens’ Sara Khalaf shows why automated IP checking matters for advanced SoC design.

Arteris’ Tim Schneider digs into hardware/software interface consistency for RTL, drivers, verification, documentation, and firmware.

Cadence’s Reela Samuel discusses how 3D-ICs bring logic, memory, and accelerators into tight physical proximity.