tag: Siemens EDA

AI Agents Need Goals
By Brian Bailey - 16 Apr, 2025 - Comments: 0

Experts At The Table: Definitions and goals matter when it comes to using AI effectively, and it has to be tightly reined in to be effective. Semiconductor Engineering sat down with a panel of experts to discuss these issues and others, including Johannes Stahl, senior director of product line management for the Systems Design Group at Synopsys; Michael Young, director of product marketing for ... » read more

Chiplet Tradeoffs And Limitations
By Ann Mutschler - 10 Apr, 2025 - Comments: 0

The semiconductor industry is buzzing with the benefits of chiplets, including faster time to market, better performance, and lower power, but finding the correct balance between customization and standardization is proving to be more difficult than initially thought. For a commercial chiplet marketplace to really take off, it requires a much deeper understanding of how chiplets behave indiv... » read more

Implementing AI Activation Functions
By Bryon Moyer - 10 Apr, 2025 - Comments: 1

Activation functions play a critical role in AI inference, helping to ferret out nonlinear behaviors in AI models. This makes them an integral part of any neural network, but nonlinear functions can be fussy to build in silicon. Is it better to have a CPU calculate them? Should hardware function units be laid down to execute them? Or would a lookup table (LUT) suffice? Most architectures inc... » read more

3D-IC Ecosystem Starts To Take Form
By Brian Bailey - 10 Apr, 2025 - Comments: 0

The adoption of chiplets is inevitable, but exactly when a mass migration toward this design approach will begin is yet to be determined. Nevertheless, some of the biggest technological and business-related barriers are being addressed. And while a chiplet-based design remains beyond the economic reach of many companies today, that is starting to change. Early signs of an emerging ecosystem ... » read more

Shift Left In DFT Design
By Jeff Mayer - 08 Apr, 2025 - Comments: 0

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to maintain high productivity and quality throughout the design flow. This keeps projects on schedule, within budget, and ensures they remain high-quality, reliable, yield well and perform as intended. ... » read more

Chip Aging Opens Up New Attack Vectors
By Adam Kovac - 03 Apr, 2025 - Comments: 0

The longer a piece of silicon is out in the field the more prone it becomes to a cyberattack, raising questions about the optimal longevity of circuits and the impact of extending their lifetimes. This is particularly challenging for safety- and mission-critical applications, where the cost of development can run as high as $100 million for some of the most complex designs. Chipmakers want t... » read more

HyperLynx
By Siemens EDA - 03 Apr, 2025 - Comments: 0

You gain the full power of HyperLynx when it is fully integrated as part of the Xpedition PCB design flow. Yet, it also interfaces with most PCB layout tools, allowing any engineer to quickly import and set up their PCB designs for analysis, regardless of their existing toolset. And because its progressive verification methodology analyzes a design in stages, HyperLynx locates issues earlier an... » read more

Blog Review: Apr. 2
By Jesse Allen - 02 Apr, 2025 - Comments: 0

Synopsys’ Meenakshy Ramachandran explores how DisplayPort Automotive Extensions help meet functional safety and security standards for the increasingly higher-resolution and more immersive in-vehicle displays in connected, autonomous, shared, and electric vehicles. Siemens’ Gabriella Leone and Michael Munsey discuss the need for a collaborative semiconductor business platform and how to ... » read more

How AI And Connected Workflows Will Close The Verification Bottleneck
By Harry Foster - 27 Mar, 2025 - Comments: 0

For decades, verification has been the unsung hero of chip development—quietly catching bugs before they reach silicon. But as semiconductor complexity has skyrocketed, verification has turned into the bottleneck of development cycles. This challenge has a name: Verification Productivity Gap 2.0. Back in the early 2000s, the Verification Productivity Gap 1.0 emerged when design complexi... » read more

Challenges In Managing Chiplet Resources
By Ann Mutschler - 27 Mar, 2025 - Comments: 0

Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

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