tag: Siemens EDA

Why Chips Fail, And What To Do About It
By Ed Sperling - 11 Dec, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips in the context of safety- and mission-critical systems, as well as increasing utilization due to an explosion in AI data, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verificat... » read more

Verifying SRAM Yield Inclusive Of Rare And Random Defects
By Siemens EDA - 11 Dec, 2024 - Comments: 0

Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone. Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell. This work presents a novel method to enable the inclusion of ... » read more

Silicon Lifecycle Management Gains Steam
By Laura Peters - 10 Dec, 2024 - Comments: 0

Silicon lifecycle management (SLM) is gaining significant traction, driven increasingly by stringent reliability requirements for safety-critical devices in aerospace, medical, and automotive. Improving reliability has been a discussion point for years, but it has become especially important with the use of chips designed at leading-edge nodes in both mission- and safety-critical application... » read more

ESD Verification For 2.5D And 3D-ICs
By Siemens EDA - 10 Dec, 2024 - Comments: 0

Ensuring your integrated circuit (IC) design can withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. The new automated ESD ... » read more

Testing For Thermal Issues Becomes More Difficult
By Gregory Haley - 10 Dec, 2024 - Comments: 0

Increasingly complex and heterogeneous architectures, coupled with the adoption of high-performance materials, are making it much more difficult to identify and test for thermal issues in advanced packages. For a single SoC, compressing higher functionality into a smaller area concentrates the processing and makes thermal effects more predictable. But that processing can happen anywhere in a... » read more

Efficient ESD Verification For 2.5/3D Automotive ICs
By Dina Medhat - 09 Dec, 2024 - Comments: 0

Protection against electrostatic discharge (ESD) events is an extremely important aspect of integrated circuit (IC) design and verification, particularly for 2.5/3D designs targeted for automotive systems. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical ... » read more

Auto Chip Aging Accelerates In Hot Climates
By Ed Sperling - 09 Dec, 2024 - Comments: 1

Automotive chips are aging significantly faster than expected in hot climates with sustained high temperatures, raising concerns about the reliability of electrified vehicles over time and whether advanced-node chips are the right choice for safety-critical applications. Many of the most advanced electronics used in vehicles today are ASIL D-compliant, expected to function up to 125° C. But... » read more

Where Cryptography Is Headed
By Adam Kovac - 05 Dec, 2024 - Comments: 0

Reports began surfacing in October that Chinese researchers used a quantum computer to crack military-grade AES 256-bit encryption. Those reports turned out to be wrong, but that did little to dampen concerns about what would happen if it was true. The looming threat of quantum computers breaking today's encryption, and the stockpiling of encrypted data in preparation for a time when it can ... » read more

Blog Review: Dec. 4
By Jesse Allen - 04 Dec, 2024 - Comments: 0

Siemens' Reetika explains how creating and verifying a complete reset tree structure allows designers to trace the flow of reset signals across the design and ensure that every sequential element is tagged correctly within its respective reset domain. Cadence's Durlov Khan suggests DDR5 DIMM Memory Models and Discrete Component Models as part of a flexible approach to validating specific com... » read more

Chip Companies Play Bigger Role In Shaping University Curricula
By Liz Allan - 02 Dec, 2024 - Comments: 0

A shortage of senior engineers with the necessary skills and experience is forcing companies to hire and train fresh graduates, a more time-consuming process but one that allows them to rise through the ranks using the companies' preferred technology and systems. Universities and companies share the goal of helping a graduate become productive in the workplace as quickly as possible, and the... » read more

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