Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster


By Nermeen Hossam and John Ferguson Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a chip is DRC-clean to start their chip assembly and verification. Today’s SoC designers typically start chip integration in parallel with block development.... » read more

Verification Scorecard: How Well Is The Industry Doing?


Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Is There A Limit To The Number of Layers In 3D-NAND?


Memory vendors are racing to add more layers to 3D NAND, a competitive market driven by the explosion in data and the need for higher-capacity solid state drives and faster access time. Micron already is filling orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin volume manufacturing 238-layer 512Gb triple level cell (TLC) 4D NAND in the first half of next... » read more

Power Methodology For Estimation And Optimization In The ASIC/SoC Flow


In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible... » read more

AI Power Consumption Exploding


Machine learning is on track to consume all the energy being supplied, a model that is costly, inefficient, and unsustainable. To a large extent, this is because the field is new, exciting, and rapidly growing. It is being designed to break new ground in terms of accuracy or capability. Today, that means bigger models and larger training sets, which require exponential increases in processin... » read more

Cloud-Ready Circuit Simulation Accelerates SoC Verification


By Nebabie Kebebew and Nigel Bleasdale Driven by the explosion of big data and expanding applications, chip design complexity is increasing. Applications such as high-performance computing (HPC), the Internet of Things (IoT), automotive, and 5G mobile and communications coupled with advanced process technology nodes require running a large number of circuit simulations to ensure the circuits... » read more

New Uses For AI In Chips


Artificial intelligence is being deployed across a number of new applications, from improving performance and reducing power in a wide range of end devices to spotting irregularities in data movement for security reasons. While most people are familiar with using machine learning and deep learning to distinguish between cats and dogs, emerging applications show how this capability can be use... » read more

Verifying A DDR5 Memory Subsystem


With the increasing complexity of DDR memory models and a vast set of configurations, it has become a daunting experience for verification engineers to verify memory subsystems. With the help of DDR5 Questa VIP and its unique features, engineers can maximize their debugging capabilities and achieve their verification goals quickly and efficiently. This paper introduces the Siemens EDA DDR5 and ... » read more

Design And Security Challenges for VR


Virtual reality is no longer just for gamers, and as this technology is deployed in everything from health care to industrial training, the requirements for processing more data faster over a high-speed connection are growing. Designing these devices continues to be a study in contradictions. They must be extremely low power, with a small enough batteries to make them comfortable to wear. Bu... » read more

Blog Review: Aug. 10


Siemens' Heather George provides a primer on 3D IC, including the problems it is trying to solve, what differentiates it from other multi-chip technologies, and some of the unique challenges in 3D integration. Cadence's Paul McLellan shares highlights from the Automobil Elektronik Kongress, including how the increasing amount of software in a car is driving disruption in the automotive suppl... » read more

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