tag: Siemens

Critical Area-Based Test Pattern Optimization For High-Quality Test
By Mentor, a Siemens Business - 02 Sep, 2020 - Comments: 0

Among the challenges for DFT engineers is how to set a target metric for ATPG and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected doesn’t consider the likelihood of one fault occurring compared to another. Tessent developed total critical area ATPG technology that enables the sorting and ordering of patterns based on their likelihood... » read more

Components For Open-Source Verification
By Brian Bailey - 02 Sep, 2020 - Comments: 2

Defining an open-source verification methodology is a lot more difficult than just developing an open-source simulator. This is the reality facing open-source hardware such as RISC-V. Some people may be asking for the corresponding open-source verification, but that is a much tougher problem — and it is not going to be solved in the short term. Part one examined the reasons why open-source... » read more

Blog Review: Sept. 2
By Jesse Allen - 02 Sep, 2020 - Comments: 0

Arm's Pranay Prabhat highlights research into zero-power or low-power sensing devices and work toward designing a microcontroller that could fit with DARPA N-ZERO sensors. Mentor's Shivani Joshi provides a primer on the ODB++ standard data exchange file format that generates PCB design data files for use in fabrication, assembly, and test. Cadence's Paul McLellan shares some highlights fr... » read more

New Architectures, Much Faster Chips
By Ed Sperling and Ann Mutschler - 31 Aug, 2020 - Comments: 0

The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

Challenges In Using AI In Verification
By Ann Mutschler - 27 Aug, 2020 - Comments: 0

Pressure to use AI/ML techniques in design and verification is growing as the amount of data generated from complex chips continues to explode, but how to begin building those capabilities into tools, flows and methodologies isn't always obvious. For starters, there is debate about whether the data needs to be better understood before those techniques are used, or whether it's best to figure... » read more

The Evolution Of High-Level Synthesis
By Brian Bailey - 27 Aug, 2020 - Comments: 3

High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Radio Frequency Technology Is Found Everywhere In Daily Life
By Greg Curtis - 27 Aug, 2020 - Comments: 0

By Greg Curtis and YuLing Lin Innovation is everywhere around us. From high-performance computing, communications, autonomous driving, and the Internet of Things (figure 1), each segment has led to a rapid increase in design innovation. This innovation has been particularly true in communications, as Radio Frequency (RF) technology is found everywhere in daily life. RF technology is critical... » read more

Accelerate Time To Market With Calibre nmLVS-Recon Technology
By Mentor, a Siemens Business - 27 Aug, 2020 - Comments: 0

One thing is clear…tapeouts are getting harder, and taking longer. As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS-Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market. To rea... » read more

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Blog Review: Aug. 19
By Jesse Allen - 19 Aug, 2020 - Comments: 0

Rambus' Scott Best digs into some of the most sophisticated attacks used to target and compromise security chips, such as laser voltage probing, focused ion beam editing, reverse engineering, and NVM extraction, and ways to counter them. Synopsys' Chris Clark proposes a way to identify problems earlier and better ensure safety and reliability in automotive SoCs by moving from a linear develo... » read more

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