tag: simulation

IMEC Partner Technical Week Review
By Aurélie Juncker - 23 Jun, 2016 - Comments: 0

In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every six months to present scientific results to their partners. During this week, a number of specialists from IMEC's many partner companies also discuss their progress in areas related to IM... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 15 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 09 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together
By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

Formal Confusion
By Brian Bailey - 07 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the right and wrong ways to apply formal verification technology with Normando Montecillo, associate technical director at [getentity id="22649" comment="Broadcom"]; Ashish Darbari, principal engineer at [getentity id="22709" e_name="Imagination Technologies"]; Roger Sabbagh, principal engineer at Huawei; and Stuart Hoad, lead engineer at PMC Sierra... » read more

DAC Day Two: Down To Business
By Brian Bailey - 07 Jun, 2016 - Comments: 0

DAC day two started with a breakfast presentation put on by Synopsys which included guests from ARM, TSMC and HiSilicon. It was titled Collaborating to Enable Design with the latest processors and finFET processes. Collaboration is a word that we hear increasingly when talking about the advanced nodes and today we are truly at the point where one company cannot do it all. Ron Moore, VP of ma... » read more

Valtrix Pushes For Horizontal Verification Reuse
By Brian Bailey - 01 Jun, 2016 - Comments: 0

Some of the most significant advances are not the result of a single person or a single idea. They often don’t happen overnight, and are suggested by a change that slowly becomes pervasive enough to become a generalized solution. That is exactly what is happening right now in the area of functional verification. The tools and methodologies in place at the moment assumed designs typical of the... » read more

Formal Confusion
By Brian Bailey - 26 May, 2016 - Comments: 0

Formal verification has come a long way in the past five years. Tool developers changed direction and started to create self-contained apps which have led to a rapid proliferation of the technology. But formal is a diverse set of tools that can solve a variety of problems in the verification space and this has created a different kind of confusion within the industry. To find out how the indust... » read more

Virtual Modeling With Aldec And Imperas
By Aldec - 25 May, 2016 - Comments: 0

Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software... » read more

Synopsys Buys Simpleware
By Ed Sperling - 20 May, 2016 - Comments: 0

Synopsys bought [getentity id="22916" comment="Simpleware"], which makes tools for turning 3D images into models that can be used in simulation. The deal extends [getentity id="22035" e_name="Synopsys"] into a spectrum of new markets, including medical, dental, oil and gas and even food sciences and archaeology. While the company still has a play in computer-aided engineering and design, Sim... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy