tag: SoC

IP Subsystems: What Works, What Doesn’t
By Ann Mutschler - 21 Aug, 2014 - Comments: 0

The [getkc id="81" kc_name="SoC"] landscape has changed substantially over the past decade and so have some of the definitions for aspects of the system—particularly the [getkc id="43" kc_name="IP"] subsystem. “We’ve been at the point for some time for large SoCs that what we thought about as a building block 10 years ago is now too small,” said [getperson id="11489" p_name="Drew Win... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

Tech Talk: Photonics, Take 2
By Ed Sperling - 23 Jun, 2014 - Comments: 0

Mentor Graphics’ John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the second part in a two-part series. [youtube vid=4-5FbxIpIk4] To view part 1, click here. » read more

It’s All IP In An SoC
By Ernest Worthman - 05 Jun, 2014 - Comments: 1

[getkc id="43" comment="IP"] (IP) has become the major building blocks of complex, highly integrated systems on chips ([getkc id="81" kc_name="SoC"]s), which are found in almost every modern, intelligent electronic device. They have evolved into a one-chip solution that manages many to all of the functions, features, and applications that are found in the ubiquitous sea of today’s electronic... » read more

IP To Meet 2.5D Requirements
By Ann Mutschler - 08 May, 2014 - Comments: 1

The semiconductor industry is still in the early stages of evolution in the realm of 2.5D, but when these devices do come out, the IP used on them will have to be brand new, according to Javier DeLaCruz, senior director of engineering at eSilicon. “The IP causes the biggest risk that you’re going to have in this implementation,” he said. “Everything else in here for making those ASIC... » read more

New Approaches For Reliability
By Ed Sperling - 28 Mar, 2014 - Comments: 0

The definition of reliability hasn’t budged since the invention of the IC, but how to achieve it is starting to change. In safety-critical systems, as well as in markets such as aerospace, demands for reliability are so rigorous that they often require redundant circuitry—and for good reason. A PanAmSat malfunction in 1998 caused by tin whisker growth wiped out pagers for 45 million use... » read more

How Much Will That Chip Cost?
By Ed Sperling - 27 Mar, 2014 - Comments: 1

From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those proce... » read more

Big Shift In SoC Verification
By Ed Sperling - 06 Mar, 2014 - Comments: 5

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
By Various Writers - 29 Jan, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

The Next Big Threat: Power And Performance
By Ed Sperling - 17 Jan, 2014 - Comments: 3

In the shiny world of consumer electronics and powerful computers, taking a grinder to the outside of a package may sound more like safecracking than sophisticated electronic code hacking. The reality is there is more in common than most semiconductor companies would like to admit, and the starting point often is just as crude. To no small extent, systems on chip have become miniature safes.... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy