Managing Quality With Developer Desktop Analysis


Even the most seasoned developer is prone to introducing a few new bugs in new or modified code. Static analysis is a great solution to help development teams find and fix those issues. Now with Coverity’s new desktop analysis capabilities, developers can find and fix their own defects before checking their code into the source control management system – and before anyone else finds the de... » read more

New Architectures, Approaches To Speed Up Chips


The need for speed is back. An explosion in the amount of data that needs to be collected and processed is driving a new wave of change in hardware, software and overall system design. After years of emphasizing power reduction, performance has re-emerged as a top concern in a variety of applications such as smarter cars, wearable devices and cloud data centers. But how to get there has cha... » read more

Why Instrumentation Isn’t Optional


When writing code it is often useful to add informational statements that give an insight into control flow and data management as well as aiding in observation of the actual code at runtime. As such, instrumentation is an important component of code running on a live system. The proliferation of "printf" debug statements, whereby data is output to a console, is testament to this. Sending te... » read more

Executive Insight: Aart de Geus


Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to discuss Moore's Law, the IoT, inflection points and how chip design will evolve in coming years. SE: We are in the middle of possibly one of the biggest transition points we’ve ever seen in this industry. How do you envision things shaking out? De Geus: There is no question that there is an enormou... » read more

New Starting Point


Debate has been raging for years about whether software or hardware should be the starting point for improving power and performance, or whether it should elevated another notch by fusing hardware and software into a system-level approach. Now, groups like Leti, IEEE, SEMI, and a number of researchers in leading universities around the globe are beginning to talk about moving the starting point... » read more

No More Easy IP Money


The semiconductor intellectual property ([getkc id="43" kc_name="IP"]) industry is two decades old, but questions are still being asked about what's wrong with it and what needs to be fixed. Normally these kinds of issues are reserved for fast-moving, young industries, not one that is the backbone of semiconductors. Design reuse has become an indispensable part of the design of nearly all el... » read more

Designing An Efficient DSP Solution


A look at the key challenges in DSP implementation from both hardware and software application perspectives, and how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specia... » read more

Cars, Security, And HW-SW Co-Design


Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Executive Insight: Raik Brinkmann


[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down with Semiconductor Engineering to discuss where and why formal verification is gaining traction, and how it fits alongside other verification approaches. What follows are excerpts of that conversation. SE: [getkc id="33" kc_name="Formal"] has been around for a whi... » read more

Can Verification Meet In The Middle?


Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

← Older posts Newer posts →