tag: software

Virtualization Revisited
By Ernest Worthman - 05 May, 2016 - Comments: 0

Virtual instruction set computing (VISC) is getting a second look as power and performance improvements begin to slow and [getkc id="74" comment="Moore's Law"] is supplanted by [getkc id="279" comment="Koomey's Law"]. While the current crop of [getkc id="185" kc_name="finFETs"] will likely be extended for at least one more process node, there is some debate about what comes next, whether tha... » read more

Rethinking Processor Architectures
By Ed Sperling - 05 May, 2016 - Comments: 2

The semiconductor industry's obsession with clock speeds, cores and how many transistors fit on a piece of silicon may be nearing an end for real this time. The [getentity id="22048" comment="IEEE"] said it will develop the International Roadmap for Devices and Systems (IRDS), effectively setting the industry agenda for future silicon benchmarking and adding metrics that are relevant to specifi... » read more

Turning Verification Inside Out
By Neil Johnson - 02 May, 2016 - Comments: 0

A new motivation for rebalancing came to me during a conversation I had a couple weeks ago at the Agile Alliance Technical Conference. I had the chance to compare my day-to-day responsibilities with those of Lisa Crispin. Lisa is a software test expert that is very well regarded within the [getkc id="182" comment="Agile Development"] community. Think of her as a Harry Foster/Janick Bergeron typ... » read more

Automating System Design
By Ann Mutschler - 02 May, 2016 - Comments: 1

Change is underway in the chip design world, creating opportunities and challenges that reach far beyond questions about whether Moore’s Law is slowing or stopping. Never before in the history of semiconductors has design been so complex and sophisticated, and never has it touched so many lives in so many interesting ways. This is all happening as a result of the chip’s enabling role in ... » read more

Rightsizing Challenges Grow
By Ed Sperling - 20 Apr, 2016 - Comments: 0

Rightsizing chip architectures is getting much more complicated. There are more options to choose from, more potential bottlenecks, and many more choices about what process to use at what process node and for which markets and price points. Rightsizing is a way of targeting chips to specific application needs, supplying sufficient performance while minimizing power and cost. It has been a to... » read more

The Next Big Challenge
By Ed Sperling - 07 Apr, 2016 - Comments: 0

In his keynote speech at the Synopsys User Group last month, company chairman and co-CEO Aart de Geus defined IoT as the Internet of Threats. As interviews across the semiconductor industry have revealed over the past 12 months, his comment was very much on target. As more things are connected—and that includes everything from watches to toasters to cars to buildings within a city—securi... » read more

White-Box Crypto Gains Traction
By Ernest Worthman - 07 Apr, 2016 - Comments: 0

Ask any cryptography expert which is better, hardware- or software-based cryptography, and they'll almost always choose the hardware. But as the IoE begins to take root in cost-sensitive markets with tight market windows, that won't always be an option. Plan B is software cryptography, which historically has been used at the application level in the form of anti-virus, anti-spyware, and soft... » read more

Coherency, Cache And Configurability
By Ann Mutschler - 24 Mar, 2016 - Comments: 0

Coherency is gaining traction across a wide spectrum of applications as systems vendors begin leveraging heterogeneous computing to improve performance, minimize power, and simplify software development. Coherency is not a new concept, but making it easier to apply has always been a challenge. This is why it has largely been relegated to CPUs with identical processor cores. But the approach ... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

What’s Next for System-Level Power Modeling?
By Alan Gibbons - 23 Mar, 2016 - Comments: 1

Availability of models and libraries has long been one of the biggest barriers to the adoption of new EDA tools and methodologies, whether due to the investment needed to create these models and libraries or because of the “at-risk” nature of developing complex models in proprietary formats. With the approval of UPF3.0 (IEEE 1801-2015) this past December, we now have an industry standar... » read more

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