EDA Challenges Machine Learning


Over the past few years, [getkc id="305" kc_name="machine learning"] (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. While there is clearly a lot of hype surrounding this, it appears that machine learning can produce a better outcome for many tasks in the EDA flow than even the... » read more

Power Is A Global Issue


Power is now the No. 1 target in developing chips. In a keynote speech at the recent Cadence Verification Summit, James “Jim” Hogan—an EDA investor associated with companies such as Sonics, Nimbic, Solido, AutoESL, Altos and many others, and previously part of Cadence’s Telos venture arm—made the point that power is the big problem that needs to be solved. We all know that reducing... » read more

Corners Up, Margins Down


By Ed Sperling Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC. The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on ... » read more