Making Hardware Design More Agile


Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

Taking Stock Of IoT Standards


Trying to make sense of [getkc id="76" comment="Internet of Things"] standards today is like opening a can of worms. Definitions are still shaking out, consortia are popping up quickly, and everyone is in a mad scramble to capture their piece of the much lauded potential of an intimately connected world of devices. With so many points to consider, security is a good place to start. It is ... » read more

Who’s Calling The Shots


Throughout the PC era and well into the mobile phone market, it was semiconductor companies that called the shots while OEMs followed their lead and designed systems around chips. That’s no longer the case. A shift has been underway over the past half decade, and continuing even now, to reverse that trend. The OEM — or systems company as it is more commonly called today — now determine... » read more

Making Hardware Design More Agile


Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

Executive Insight: Grant Pierce


Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to talk about the effects of industry consolidation, China's impact, and the unfolding security threat with the IoT. What follows are excerpts of that interview. SE: Consolidation is one of the big stories right now. What does that mean for your company and the industry as a whole? Pierce: It's a very inter... » read more

The Week In Review: Design/IoT


The EDA Consortium announced EDA industry revenue increased 7.5% for Q1 2015 to $1877 million, compared to $1746.1 million in Q1 2014. The four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 8.0%. Employment also increased, and according to Wally Rhines, "all categories showed revenue increases except CAE. Geographically, the Ameri... » read more

The Week In Review: Design/IoT


IP Sonics released the latest version of the company's flagship NoC, which expands on their interleaved multi-channel technology and includes new layout optimization features for design flows based on modern physical synthesis and place & route tools. Synopsys extended its PCI Express 4.0 IP to support RAS features to help designers ensure data integrity and increase data protection i... » read more

What Is A System Now?


Defining a system used to be relatively straightforward. But as systems move onto chips, and as those chips increasingly are connected with applications and security spanning multiple devices, the definition is changing. This increases the complexity of the design process itself, and it raises questions about how chips and software will be designed and defined in the age of the [getkc id="76... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions Synopsys announced Sunday it would acquire privately held formal verification provider Atrenta, for an undisclosed sum. That was followed quickly by Ansys' announcement that it would buy data analytics firm Gear Design Solutions. Tools IC Manage uncorked its big data predictive analytics tool Envision, which provides real-time design progress analytics to pre... » read more

The Interconnect Bottleneck


With communications playing a crucial role in the design and performance of multi-core SoCs, various interconnect structures have been proposed as promising solutions to simplify and optimize SoC design. However, sometimes things don’t go as planned and the interconnect becomes the bottleneck. “Under high utilization cases the DRAM will be over-constrained with requests from all the a... » read more

← Older posts Newer posts →