The Week In Review: Design/IoT

IP updates from Sonics and Synopsys; NXP’s plug-and-play NFC chip; UMC process qualifications; Ansys at the races; Synopsys teams with universities for IoT labs in Taiwan.



Sonics released the latest version of the company’s flagship NoC, which expands on their interleaved multi-channel technology and includes new layout optimization features for design flows based on modern physical synthesis and place & route tools.

Synopsys extended its PCI Express 4.0 IP to support RAS features to help designers ensure data integrity and increase data protection in cloud computing SoCs. The new RAS features increase system reliability by using parity and error correcting code (ECC) data protection in conjunction with protocol-defined mechanisms to detect and correct errors in the datapath and RAMs.


NXP introduced a plug-and-play chipset for NFC that features an NFC contactless reader IC and embedded firmware with integrated communication protocols relevant for NFC, optimized for Linux and Android.


UMC will tape out process qualification vehicle test chips for its 14nm FinFET process with ARM’s Cortex-A family core and Synopsys’ embedded memory IP and the Memory System test and repair solution.

Drayson Racing Technologies utilizes ANSYS’ suite of electronics simulation software in the development of its high-performance electric drivetrains and wireless electric vehicle charging systems.

Synopsys teamed up with National Taiwan University, National Cheng Kung University, National Tsing Hua University, and National Chiao Tung University to establish joint advanced design labs for Internet of Things applications at the schools. This is the first cooperation between a foreign semiconductor design software and IP company and top universities in Taiwan to focus on advancing IoT ecosystem business opportunities and research and development.

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