tag: Sonics

IP And FinFETs At Advanced Nodes
By Ed Sperling - 31 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta. What follows are excerpts of that conversation. SE: It’s harder for a fabless semiconductor ... » read more

The Week In Review: Design
By Ed Sperling - 25 Jul, 2014 - Comments: 0

Tools Sonics upgraded its on-chip network, improving support for memory subsystems as well as performance with guaranteed bandwidth allocation across multiple SOC flows. The company said these upgrades add support for the latest DDR4 and LPDDR4 memories, for the multi-threading capabilities of the Open Core Protocol interface, and while adding non-blocking concurrency technologies. Mentor G... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

New Winners And Losers
By Brian Bailey - 24 Jul, 2014 - Comments: 0

During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 21 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation. SE: What happens with the next revs of finFET... » read more

After Moore’s Law: More With Less
By Brian Bailey - 10 Jul, 2014 - Comments: 6

In the decades when Moore’s Law went unquestioned, the industry was able to migrate to the next smaller node and receive access to more devices that could be used for increased functionality and additional integration. While less significant transistor-level power savings have been seen from the more recent nodes, as leakage currents have increased, the additional levels of integration have b... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 10 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Bernard Murphy, CTO of Atrenta; Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics. What follows are excerpts of that conversation. SE: As we push into the next nodes, we’ve got a ... » read more

Locking Down The Chip
By Ernest Worthman - 09 Jul, 2014 - Comments: 0

The push toward securing chips is complicated by the amount of third-party IP that is being used inside of today’s complex SoCs. This has cast new light on the potential for on-chip networks to also function in securing signals that flow through those networks. This becomes particularly important with the Internet of Things, because the source of those signals isn’t always obvious to the... » read more

Moore’s Law Tail No Longer Wagging The Dog
By Brian Bailey - 26 Jun, 2014 - Comments: 3

In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to ut... » read more

Asynchronous Is Mostly Academic
By Ann Mutschler - 26 Jun, 2014 - Comments: 4

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and asynchronous logic. Asynchronous logic promises a number of benefits in some specific application areas, and one that buoys to the surface for potential near-term use is in the area of security a... » read more

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