Tempus Timing Signoff Solution

By Cadence - 23 Nov, 2022 - Comments: 0

The Cadence Tempus Timing Signoff Solution is the fastest static timing analysis (STA) tool in the industry today with unique distributed processing and cloud capabilities enabling hundreds of CPUs to quickly complete even the largest designs. With full foundry certification and a comprehensive set of advanced capabilities, the Tempus solution delivers SPICE-accurate results to hundreds... » read more

Next-Generation Distributed Static Timing Analysis On The Cloud

By Ajit Sequeira - 26 May, 2022 - Comments: 0

Ever-growing chip size and complexity put pressure on every step and every electronic design automation (EDA) tool in the development flow. More decisions must be made at the architectural stage, stressing virtual prototypes and high-level models. Simulations become slower and consume more memory. Formal verification struggles to achieve full proofs. Logic synthesis and layout have a harder tim... » read more

Timing Library LVF Validation For Production Design Flows

By WeiLii Tan - 27 Feb, 2020 - Comments: 3

Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

Which Glitch Is Which?

By Pat Sheridan - 25 Jul, 2019 - Comments: 0

Glitch is a commonly used term in modern vernacular, used to identify unexpected problems in everything from the space race, web site down time, or a crash of your latest mobile phone app. In electronics design glitch has a more specific meaning, referring to unnecessary signal transitions in a combinational circuit. Eliminating this extra switching activity can save power consumption, especial... » read more

Next-Generation Liberty Verification And Debugging

By WeiLii Tan - 27 Sep, 2018 - Comments: 1

Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

“Good Enough For Government Work?” Not Anymore.

By Ruben Molina - 26 Jul, 2018 - Comments: 0

When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with the company; some of them for as many as 40 years. To get an idea of how many people I’m talking about, there was a retirement party for at least 3 or 4 people every week just in our division. You can imagine tha... » read more

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tag: STA

Tempus Timing Signoff Solution

Next-Generation Distributed Static Timing Analysis On The Cloud

Timing Library LVF Validation For Production Design Flows

Which Glitch Is Which?

Next-Generation Liberty Verification And Debugging

“Good Enough For Government Work?” Not Anymore.

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