tag: standards

Bridging The IP Divide
By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

Unexpected Security Holes
By Ed Sperling - 13 Apr, 2016 - Comments: 0

Security is emerging as one of the top challenges in semiconductor design across a variety of markets, with the number of security holes growing by orders of magnitude in sectors that have never dealt with these kinds of design constraints before. While security has been a topic of conversation for years in mobile phones and data centers, commercial and industrial equipment is being connecte... » read more

Planes, Cars, And Lagging Standards
By Ed Sperling - 28 Mar, 2016 - Comments: 0

Automotive and aerospace standards are struggling to adapt to pervasive connectivity, increased functionality, and new packaging approaches and architectures, leaving chipmakers and systems vendors unsure about what needs to be included in future designs. Each of these markets has a reputation for being lumbering and unresponsive, in part because they deal with safety-critical issues and i... » read more

Tech Talk: ADAS
By Ed Sperling - 23 Mar, 2016 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris, explains what the Advanced Driver Assistance Systems standard is, where the problems are, and why this is becoming so important in automotive semiconductor design. » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Tech Talk: ISO 26262
By Ed Sperling - 24 Feb, 2016 - Comments: 0

Arteris' Kurt Shuler talks about the automotive design standard, how it applies to semiconductors, and where engineers run into problems. » read more

Powerful New Standard
By Brian Bailey - 11 Feb, 2016 - Comments: 0

In December the IEEE released the latest version of the 1801 specification, entitled the IEEE standard for design and verification of low-power integrated circuits. Most people know it as UPF, or the Unified Power Format. That was the name the first version of it held while being developed within Accellera. The standard provides a way to specify the power intent associated with a design, enabli... » read more

Predictions For 2016: Tools and Flows
By Brian Bailey - 28 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Power, Standards And The IoT
By Ed Sperling - 08 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power, standards and the IoT with Jerry Frenkil, director of open standards at [getentity id="22055" comment="Si2"]; Frank Schirrmeister, group director of product marketing of the System Development Suite at [getentity id="22032" e_name="Cadence"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"]; and Vojin Zivojno... » read more

One Flow To Rule Them All
By Brian Bailey - 12 Nov, 2015 - Comments: 0

The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

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