Chip Industry Week In Review


GlobalFoundries will create a new center for advanced packaging and testing of U.S.-made essential chips within its New York manufacturing facility. A flurry of announcements on advanced semiconductors and AI rolled out this week as U.S. President Biden wrapped up his term: The Biden-Harris Administration released an Interim Final Rule on Artificial Intelligence Diffusion to strengthen ... » read more

Transformation Of Polarons As Tellurene Becomes Thinner


A new research paper titled "Thickness-dependent polaron crossover in tellurene" was published by researchers from Rice University, Lawrence Berkeley National Laboratory, MIT, Argonne National Laboratory, ORNL, Purdue University, and Stanford University. Abstract "Polarons, quasiparticles from electron-phonon coupling, are crucial for material properties including high-temperature supercond... » read more

Chip Industry Week In Review


SK hynix started mass production of 1-terabit  321-high NAND, with availability scheduled for the first half of next year. Rapidus will receive an additional ¥200 billion yen ($1.28B) from the Japanese government beginning in fiscal year 2025, reports Nikkei. This is on top of ¥920 billion yen ($5.98B) Rapidus has already received from the government in support of its goal to reach commer... » read more

Chip Industry Technical Paper Roundup: Oct. 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=371 /]   More Reading Chip Industry Week In Review AI CPU chiplet platform; Intel-AMD pact; GDDR7 DRAM; AI-RFIC funding; CHIPS Act awards; NoC tiling; thermal modeling on chiplets; $900M nuclear tech and more. Technical Paper Library home » read more

Chip Industry Week In Review


Arm joined forces with Korea's Samsung Foundry, ADTechnology, and Rebellions to create a CPU chiplet platform for AI training and inference. The new chiplet will be based on Samsung's 2nm gate-all-around technology. Intel and AMD, arch competitors for decades, formed an x86 ecosystem advisory group to collaborate on architectural interoperability and simplify software development. Samsung... » read more

3D Device With BEOL-Compatible Channel And Physical Design for Efficient Double-Side Routing


A new technical paper titled "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation, and Carnegie Mellon University. Abstract "This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves ... » read more

Research Bits: Oct. 8


Soft, flexible polymer semiconductors Stanford University materials scientists used a specialized electron microscope – cryo-electron microscopy (Cryo 4D-STEM) – to explore the microstructure of soft semiconductors that could lead to new-generation electronics. Organic mixed ionic-electronic conductors (OMIECs) are soft, flexible polymer semiconductors with promising electrochemical qua... » read more

Chip Industry Technical Paper Roundup: Oct. 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=365 /] More ReadingTechnical Paper Library home » read more

Multi-Node, Virtualized Neuromorphic Architecture


A new technical paper titled "NeuroVM: Dynamic Neuromorphic Hardware Virtualization" was published by researchers at Stanford University, UT Austin and Temsa Research & Development Center. Abstract "This paper introduces a novel approach in neuromorphic computing, integrating heterogeneous hardware nodes into a unified, massively parallel architecture. Our system transcends traditional ... » read more

Chip Industry Technical Paper Roundup: Sept. 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=358 /] More ReadingTechnical Paper Library home » read more

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