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Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?


Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero risk of unwanted surprises escaping undetected into your end-product. In order of high-to-low probability, consider: The presence of a weird-yet-entirely-possible corner-case bug Bugs “insid... » read more

Continuing Challenges For Open-Source Verification


Experts at the Table: This is the last part of the series of articles derived from the DVCon panel that discussed Verification in the Era of Open Source. It takes the discussion beyond what happened in the panel and utilizes some of the questions that were posed, but never presented to the panelists due to lack of time. Contributing to the discussion are Ashish Darbari, CEO of Axiomise; Serge L... » read more

The Problem With Post-Silicon Debug


Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more