Week in Review: IoT, Security, Auto

By Jeff Dorsch - 05 Oct, 2018 - Comments: 0

Internet of Things Amazon Web Services announced that Iridium Communications has joined the AWS Partner Network. AWS and Iridium have collaborated on development of Iridium CloudConnect, a service that enables worldwide coverage for Internet of Things applications through Iridium’s satellite network. AWS IoT is being paired with Iridium IoT services as a result. IHS Markit forecasts there wi... » read more

IP Integration Challenges Rising

By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

Reversing Course, With A Twist

By Brian Bailey - 24 Jul, 2014 - Comments: 1

Semiconductor Engineering is running an extended series of articles that examine the assertion that the end of Moore’s Law will have profound implications for the entire semiconductor, EDA and IP industries. Part one of this article, which focuses on the EDA industry, addressed the question about who was going to pay for future development of EDA tools for the latest production nodes. The ind... » read more

Asynchronous Is Mostly Academic

By Ann Mutschler - 26 Jun, 2014 - Comments: 4

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and asynchronous logic. Asynchronous logic promises a number of benefits in some specific application areas, and one that buoys to the surface for potential near-term use is in the area of security a... » read more

What’s Wrong With Power Signoff

By Ed Sperling - 12 May, 2014 - Comments: 0

Power signoff used to be a checklist item before a design went to tapeout. But as power has become a critical factor in designs, particularly at advanced nodes, signing off on power now needs to be done at multiple points throughout the design flow. That alone adds even greater complexity to already complex design processes because it requires fixed reference points and scenarios for taking mea... » read more

Powerful Memories

By Brian Bailey - 07 May, 2014 - Comments: 1

Memory consumes more of the surface area of a die than any other component. So what changes have happened over the past few years to reduce the power consumption of memories, and where are the big opportunities for saving power? Let's take a closer look. A Growing Concern One of the key drivers for SoCs is the desire to reduce product costs, reduce form factors, reduce power, increase perfo... » read more

Evolution Vs. Revolution

By Ann Mutschler - 27 Feb, 2014 - Comments: 1

In the electronic design automation industry changes to tools and flows are nearly always evolutionary. They hide as much change from the user as possible, allowing easier justification from an ROI perspective, and they raise far fewer objections from users, who don’t have to spend time learning how to use new technology or rethink tried and true approaches to problems. Revolution in chip ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer