Reversing Course, With A Twist

Reworking older nodes may provide a big boost for tools, while opening doors for investments in other areas.


Semiconductor Engineering is running an extended series of articles that examine the assertion that the end of Moore’s Law will have profound implications for the entire semiconductor, EDA and IP industries. Part one of this article, which focuses on the EDA industry, addressed the question about who was going to pay for future development of EDA tools for the latest production nodes. The industry consensus was that EDA has no choice but to perform the development and that while adoption of the new nodes may have slowed, the successful enablement of a new node will eventually attract a greater number of people.

The market is equally accepting that many people will find 28nm to be a very good target node for the foreseeable future. Many of these are companies still using some of the older nodes, such as 65nm and 40nm, so 28nm is still a significant advancement for them. The article “28nm FinFETs” discussed the increased number of active nodes and the possibility that manufacturing technologies would be migrated to the more mature nodes.

One example of new manufacturing technologies being brought in at 28nm is the adoption of fully depleted silicon on insulator (FD-SOI). “There’s a reason that FD-SOI at 28nm is getting more attention,” says Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys. “It is a change to the typical CMOS process targeted to save more on power (up to 25%) and re-establishes biasing as a viable technique to an advanced process node.”

Marco Brambilla, director of engineering for Synapse agrees: “Technologies like FD-SOI are interesting because you get the benefits of a full planar process and you get significant leakage/speed savings, especially if you can do DVFS and back-biasing.”

Existing nodes are also receiving upgrades. “We see a number of companies that are revamping their BCD (BiPolar, CMOS, DMOS) process at 180nm or 130nm for better voltage isolation, reliability, power and digital logic performance, driven by the automotive market and burgeoning IoT opportunities,” says Kevin Kranen, director of strategic alliances for Synopsys.

Production advancements bring many new possibilities for companies to consider, including those that fit into the more than Moore category. “Multi-die packaging that leverages the unique strengths of different process nodes to deliver an integrated package with capabilities beyond what could be done on a single die,” is one example Kranen cites. “Specific examples include the Xeon Phi (Knights Landing) with package on package with HMC (hybrid memory cube) and TSMC CoWoS, which offers the ability to mix logic and memory.”

Package on package (PoP), 2.5D (interposer) and 3D-IC have great promise when it comes to lowering costs for a system of heterogeneous components, which need a high level of connectivity, integration and low power. Both Xilinx and Altera have shown that a stacked-silicon interposer approach delivers higher yields and lower costs vs. a single large die. Many mobile devices already use PoP to integrate apps processor, memory and baseband. There are several other market sweet spots where packaging can be a big part of the cost reduction solution vs. single chip silicon integration. All of these will require extensions and new capabilities in EDA tools, and these efforts are in addition to the considerable developments required for the emerging nodes.

Reworking established nodes
“EDA in general is paying more attention to delivering value to designers at established nodes,” says Joseph Sawicki, vice president and general manager for the Design to Silicon Division at Mentor Graphics. “For example, some of our recent new tools in the reliability and yield learning spaces are seeing as much adoption at established nodes as they are at advanced nodes. If you can deliver tools that let people bend the economics of using an established node, you can get retooling.”

Users are also changing aspects of their design to get better results. “We are seeing much more adoption of channel length derivatives for use with leakage recovery or to reduce the number of Vt options to use, which is especially effective at 40 and 28nm process technologies,” says Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys. “With shared physical awareness optimization technology, we have seen several cases where customers were able to see congestion (or lack of) during the synthesis stage so they were able to reduce the number of metal layers used – another technique that works well on established technologies helping to reduce overall cost.”

In general, it appears as if many of the developments made for the newer nodes can have significant impacts on performance and costs associated with older nodes. “You can use process maturity and knowledge to reduce design margins,” says Kranen. “Margining can get less pessimistic as process variation becomes better understood. We’re already seeing foundries dialing in their tolerances so they can reduce margining.”

Marco Brambilla, director of engineering for Synapse agrees. “This is a node which introduces much tighter parameter spreads, meaning that yields are better, there is less need for overdesign, and this in turn becomes a PPA advantage: less die size, more speed, less power.”

“Accuracy of power noise analysis for 14/16nm is paramount given the lower supply voltage and higher power noise,” says Aveek Sarkar, vice president of product engineering and support at ANSYS. “The tool innovations that are happening enable a true chip-package co-analysis that will benefit design teams in 28nm node as they too can create accurate models of the package, connect them automatically to the chip layout, perform package-aware IC analysis and review the package and chip layout issues in the same GUI environment.”

This plays into the development of IP, as well. “Some of the knowledge ARM has received through foundry collaboration on the most advanced nodes is incorporated in second-generation 28nm physical IP, and new low-power memories for MCU applications at 55nm,” says Ron Moore, vice president of marketing for the Physical Design Group at ARM.

IP block sizes continue to increase as providers attempt to gain additional silicon area within chips. This puts pressure on some of the existing tools. “Tool capacity has not kept up,” says Marco Brambilla, director of engineering at Synapse Design. “A 14nm chip contains at least 4x the logic of a 40nm chip, but the tools do not have 4x capacity. This means the teams are bigger, which increases NRE.”

Not all agree with this statement. “The innovations necessary to handle ultra-large 14/16nm designs through distributed processing will speed up 28nm designs,” says Sarkar. “Already customers on 28nm technology nodes can see 3 to 4X speed-up when they move to the 14/16nm versions of the simulation software. So they can benefit from the reduced turn-around time to perform more analysis and get higher sign-off coverage.”

Size and complexity issues are clearly a concern for the industry. “The ability to handle large, complex IP and accurately verify the function and performance will be another challenge,” says Bruce McGaughy, chief technology officer and senior vice president of engineering of ProPlus Design Solutions. “For example, accurately characterizing and verifying large memory designs have become a huge challenge. Design challenges are increasing, especially tighter margins because of low vdd, higher variability and larger size of post layout circuits. These all require more capable tools.”

The rapid adoption of new nodes also means that some issues may not have been fully addressed when the node was new, but a slowdown in new node adoption creates an opportunity for improvements. “I believe the main improvement that is needed is in re-timing of global signals for timing closure,” says George Janac, chief executive officer for Chip Path Design Systems. “With resistance going up so fast due to narrow and thin copper wires, a signal cannot cross the chip in one cycle, but the global interconnect space is going to need this automatic functionality. This affects floorplaning, layout and verification as well.”

Not everyone sees such a bright future for EDA. “Fewer chip designs mean that EDA companies will have fewer customers from which they will generate revenue,” says Janac. “This is why Synopsys and Cadence have moved into the IP business, verification IP and software markets. Development of STAR IP, for which they can justify getting royalties from chips, is also important. Moving into the software space is another attempt to get volume revenue.”

Charlie Cheng, chief executive officer of Kilopass Technology agrees but for different reasons. “This does not bode well for the IP and EDA business. The diversification of nodes suck up more resources to do just mundane porting work, and takes away resources that could be used for innovation.”

Interestingly, Janac—while somewhat negative about the returns for the EDA industry—sees that they will use the revenue from the non-traditional EDA products to invest in additional development. “EDA companies will be able to make investments because of their multi-sourced revenue.” It remains to be seen if they use EDA as a cash cow to fund buying companies in other industries.


John Swan says:

I’m happy to see someone discussing this openly. I too have been thinking on how the slowing of Moore’s Law would impact semiconductor design methodology, including how it relates to IP. But
you have added a new twist to the discussion – the application of new process technologies to previous nodes.

Leave a Reply

(Note: This name will be displayed publicly)