28nm FinFETs?

Many companies will stay at the 28nm node for an extended period of time, but will they ultimately add finFETs to reduce current leakage.

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One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a transistor capable of getting us down to smaller geometries. On top of that they have better physical characteristics to improve operating performance, at least for some types of design.

At the same time, we are hearing that there is the potential for 28nm having an extended lifecycle, in part due to the significantly increased complexity and costs associated with double patterning at 20nm and beyond. Double patterning becomes necessary at that process geometry to enable printing of some of the smaller features. It would thus seem to be a reasonable question to ask if finFETs could be made available in a 28nm process as this would bring about some of the advantages of the new transistors without the added complexity and cost of double patterning. Semiconductor Engineering posed this question to the industry and also asked what other technologies may be included into the 28nm node.

“In 2014 there are 10 active nodes, up from 3 in 2000,” says Steve Carlson, group director of marketing at Cadence. “This has become a significant trend, with more active nodes for a semiconductor company to choose from and for EDA vendors to support. The cost-benefit analysis is a product-specific question that has led the industry to a much more fragmented foundry market.”

Looking at figures supplied by International Business Strategies (IBS), it appears as if all nodes from 65nm down through the new nodes will continue strongly through at least 2020, and even 180nm will continue to see a significant market. IBS notes that adoption rates for the newer nodes are somewhat uncertain, pointing out it is 90% probable that 10nm likely will be postponed, that cost per gate will be prohibitive, and demand will remain uncertain for devices other than high-speed processors and FPGAs.

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The path forward for the processor market is reasonably clear. “ARM is seeing the premium mobile market segment adopting FinFET process technology for power savings,” says Ron Moore, vice president of marketing for the Physical Design Group at ARM. “In a few years, the mainstream mobile market segment will see a lower cost of FinFET manufacturing and transition from 28nm to 16/14nm to take advantage of the power savings.”

But what about improvements at 28nm? “There is a lot of innovation going on at the 28nm node as foundries seek to differentiate themselves and meet customer needs for density/power/performance trade-offs,” says John Koeter, vice president of marketing for the Solutions Group at Synopsys. “You have polySiON, high-k/metal gate (multiple flavors), and FD-SOI versions of 28nm processes.”

Even without bringing the finFET back to larger nodes there are improvements that can be made. “On the manufacturing side, tools that were initially developed for advanced nodes, such as those to improve process window or runtime, are often adopted by technology followers for more mature nodes like 28nm in order to improve yield and operations” says Joseph Sawicki, vice president and general manager for the Design to Silicon Division at Mentor Graphics.

That seems to be a common theme. “28nm is still a planar CMOS process, so most of the tool improvements tend to focus on handling larger, faster designs,” says Mary Ann White, director of product marketing for the Galaxy Design Platform in Synopsys. “The bigger impact for tool change was at 20nm and below to finFET, where double patterning support and new transistor models were required.”

In fact, there does not appear to be a lot of industry support behind the idea of a 28nm finFET. “I do not think that bringing the finFET into a 28nm process would give benefits,” says Marco Brambilla, director of engineering for Synapse. “The primary reason is that it would require new process development, which is a huge investment.”

White agrees: “It might not make sense to make a finFET 28nm process since the planar transistors are effectively doing the job and the leakage between the source and drain, while worse than larger technologies, can be mitigated with leakage optimization and leakage recovery with different channel length devices.”

Brambilla also sees this last point as a negative. “FinFets make analog design much more complex, so all existing IPs would have to be redesigned and requalified, which is an investment that does not make sense.”

White notes that finFETs introduced new technology that required a lot of changes to the existing EDA tools. She cited double patterning and recognizing more parasitic extraction due to the nature of the multi-gate transistor as examples. She also points out that the number and complexity of design rules have more than doubled. Still, it is not clear how many of these are related to double patterning and how many directly to the additional complexity of the transistors.

“Usually the new technologies for smaller nodes are selected to mitigate issues in the accompanying smaller geometries,” says Kevin Kranen, director of strategic alliances for Synopsys. Kranen notes that corrugated finFETs have been around for several previous nodes. “For cost reasons these only became de rigor when planar process leakage and wire resistance dramatically reduced the benefits of planar scaling. Depending on what end-customers need, there are more economical ways to achieve the lower leakage or higher drive strength that finFETs can bring to 28nm.”

Some may see the cost benefit tradeoffs a little differently. Handel Jones, chairman and CEO of IBS, said in a white paper entitled, Why migration to 20nm bulk CMOS and 16/14nm finFETs is not the best approach for semiconductor Industry, “Intel has demonstrated the power consumption advantage of its Tri-Gate structures at 22nm, especially with its second-generation designs at 22nm such as Haswell.”

The 22nm process can support bulk planar CMOS transistors, but Intel is one company that believes it makes sense to use finFETs while others choose to stick to the old transistors. It is clear that the latest process technology developments have created more uncertainty than with any node in the past, and picking the right processes technology may be a make or break decisions for semiconductor companies and picking which process to support may be make or break for the foundries. What’s also clear is that extra costs will be borne by everyone in the short term.



  • Violoncelles

    I do not remember new technical features being implemented in previous nodes (Shallow Trench Isolation at 0.5um , Cu metals at 0.18 um , CoSilicide at 0.13 um , HKMG at 28 nm , 300 mm) . It doesn’t make sense economically

    • Brian Bailey

      I agree that we have not seen much of this in the past – anyone know of exceptions. However, having said that, if the rate of new nodes does slow down, there may be benefit in migrating manufacturing technologies back into larger nodes, just as EDA has done with many new layout technologies.

    • I agree with Brian. With the cost per transistor slowing or even rising in smaller nodes it could make sense to ‘retrofit’ a previous node. I would like to see how the FinFET vs. FD-SOI battle takes shape. Or can there be peaceful coexistence in the market?

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  • Fred

    28 nm Finfet on pre-Bulldozer versions of Athlon chips would get them up to 6 GHz, I bet. I stopped buying AMD when they stopped caring about performance per core.