Chip Industry Week In Review

By The SE Staff - 03 May, 2024 - Comments: 0

Samsung and Synopsys collaborated on the first production tapeout of a high-performance mobile SoC design, including CPUs and GPUs, using the Synopsys.ai EDA suite on Samsung Foundry's gate-all-around (GAA) process. Samsung plans to begin mass production of 2nm process GAA chips in 2025, reports BusinessKorea. UMC developed the first radio frequency silicon on insulator (RF-SOI)-based 3D IC ... » read more

Fundamental Issues In Computer Vision Still Unresolved

By Karen Heyman - 02 May, 2024 - Comments: 0

Given computer vision’s place as the cornerstone of an increasing number of applications from ADAS to medical diagnosis and robotics, it is critical that its weak points be mitigated, such as the ability to identify corner cases or if algorithms are trained on shallow datasets. While well-known bloopers are often the result of human decisions, there are also fundamental technical issues that ... » read more

Design Considerations In Photonics

By Karen Heyman - 01 May, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about what CMOS and photonics engineers need to know to successfully collaborate, with James Pond, fellow at Ansys; Gilles Lamant, distinguished engineer at Cadence; and Mitch Heins, business development manager for photonic solutions at Synopsys. What follows are excerpts of that conversation. To view part one of this discussion,... » read more

Blog Review: May 1

By Jesse Allen - 01 May, 2024 - Comments: 0

Cadence's Vatsal Patel stresses the importance of having testing and training capabilities for high-bandwidth memory to prevent the entire SoC from becoming useless and points to key HBM DRAM test instructions through IEEE 1500. In a podcast, Siemens' Stephen V. Chavez chats with Anaya Vardya of American Standard Circuits about the growing significance of high density interconnect and Ultra ... » read more

Multi-Die Design Pushes Complexity To The Max

By Ann Mutschler - 29 Apr, 2024 - Comments: 1

Multi-die/multi-chiplet design has thrown a wrench into the ability to manage design complexity, driving up costs per transistor, straining market windows, and sending the entire chip industry scrambling for new tools and methodologies. For multiple decades, the entire semiconductor design ecosystem — from EDA and IP providers to foundries and equipment makers — has evolved with the assu... » read more

Chip Industry Week In Review

By The SE Staff - 26 Apr, 2024 - Comments: 0

President Biden announced four new Workforce Hubs to support the CHIPS Act and other initiatives, in Upstate New York, Michigan, Milwaukee, and Philadelphia. The White House also provided economic context and progress updates for the President’s workforce strategy. Samsung began mass production of its ninth-gen industry-first V-NAND chip. Along with one-terabit triple-level cell design, th... » read more

EDA Looks Beyond Chips

By Ed Sperling - 25 Apr, 2024 - Comments: 0

Large EDA companies are looking at huge new opportunities that reach well beyond semiconductors, combining large-scale multi-physics simulations with methodologies and tools that were developed for chips. Top EDA executives have been talking about expanding into adjacent markets for more than a decade, but the broader markets were largely closed to them. In fact, the only significant step in... » read more

Is There Any Hope For Asynchronous Design?

By Brian Bailey - 25 Apr, 2024 - Comments: 3

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet has never resulted in more than a few experiments. Synchronous design utilizes a clock, where the clock frequency is set by the longest and slowest path in the design. That includes potential var... » read more

How To Get The Most Out Of Gate-All-Around Designs

By Andrew Appleby - 25 Apr, 2024 - Comments: 0

The semiconductor industry has relied on finFETs, three-dimensional field-effect transistors with thin vertical fins, for many generations of technology. However, the industry is reaching the limits of how much finFETs can be shrunk while maintaining their speed and power benefits, which are crucial for artificial intelligence (AI) and machine learning (ML) applications. The solution is the gat... » read more

Navigating The GPU Revolution

By Gregory Haley - 24 Apr, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the impact of GPU acceleration on mask design and production and other process technologies, with Aki Fujimura, CEO of D2S; Youping Zhang, head of ASML Brion; Yalin Xiong, senior vice president and general manager of the BBP and reticle products division at KLA; and Kostas Adam, vice president of engineering at Synopsys. What f... » read more

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tag: Synopsys

Chip Industry Week In Review

Fundamental Issues In Computer Vision Still Unresolved

Design Considerations In Photonics

Blog Review: May 1

Multi-Die Design Pushes Complexity To The Max

Chip Industry Week In Review

EDA Looks Beyond Chips

Is There Any Hope For Asynchronous Design?

How To Get The Most Out Of Gate-All-Around Designs

Navigating The GPU Revolution

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