tag: system-level design

Top 5 Trends For 2014
By Frank Schirrmeister - 19 Dec, 2013 - Comments: 0

My daughter’s and my traditional yearly cookie baking party last weekend reminded me of two things: There is still no easy recipe for system design and verification and – of course – the year is almost over again. Ouch. Let’s look back at 2013 first. Earlier this year we held a System to Silicon Verification Summit in San Jose, with an interesting technical keynote by Brian Bailey an... » read more

Rethinking Old Sayings
By Jon McDonald - 21 Nov, 2013 - Comments: 0

One of my favorite quotes from Gary Smith is a few years old: “It’s the software, stupid!” That statement was made way back in 2006. While it was, and in some ways still is, very illustrative, I believe it also points to one extreme in the back and forth between focusing on hardware then software to differentiate our electronic systems. At the point in time Gary made the statement that... » read more

Lessons From The Big Apple
By John Ellis - 24 Oct, 2013 - Comments: 0

Apple this week announced some big changes in their product lineup. Having already released their MacBook Air with the power-sipping Intel Haswell processor, Apple has made further strides with an operating system upgrade that extends battery life by yet another 10% to 15%. For those deep into technology, you may already know that low-power design capability wasn’t created overnight. It h... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 11 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of IP portfolio marketing at TS... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 04 Oct, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of ... » read more

The Rest Is History
By Jon McDonald - 26 Sep, 2013 - Comments: 0

I recently fielded some questions on the evolution of Electronic System Level design. The questions started me thinking about how ESL is being applied today and what effect some of the historical assumptions might be having on ESL’s perceived use cases. It’s interesting that we are at a point to consider historical assumptions about ESL. Looking it up, Wikipedia claims that the term ESL ... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of I... » read more

More Rigor, Please
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor companies are embracing a single-platform strategy for their SoC designs, but sifting through the options can be quite a feat. While not wildly different from the traditional derivative approach, a single-platform strategy can mean different things to different companies. Sometimes it refers to a platform that is already successful in one application ... » read more

Experts At The Table: Next-Generation IP Landscape
By Ann Mutschler - 13 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

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