tag: system-level design

System-Level Design Challenges
By Ed Sperling - 27 Aug, 2009 - Comments: 0

Prasad Subramaniam, vice president of design technology at eSilicon, talks with System-Level Design Editor Ed Sperling about the challenges at future process nodes. [youtube vid=HSgClJ9rQGk] » read more

End-User Report: Interoperability Still Lacking With System-Level Power Modeling
By Ann Mutschler - 27 Aug, 2009 - Comments: 0

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling. By Ann Steffora Mutschler SLD: How long has N... » read more

Is ESL Formal Verification An Oxymoron?
By Jon McDonald - 29 Apr, 2009 - Comments: 0

“No amount of experimentation can ever prove me right; a single experiment can prove me wrong.” – Albert Einstein I’ve had a number of conversations recently trying to understand what verification means for ESL and higher level models. It seems that most of the people I talk to are looking for a guarantee, they want formal verification, a proof that the design is doing what it should... » read more

Making Analog Easier
By Various Writers - 28 Apr, 2009 - Comments: 0

By Clive "Max" Maxfield I'm a digital design engineer by trade. All of those wibbly-wobbly effects that are characteristic of the analog domain make me nervous, and if something makes me nervous I tend to look the other way and hope it will go away. But analog isn’t going anywhere. On the contrary, the increasing amounts of analog/mixed-signal (AMS) functionality that feature in today's Sy... » read more

Experts At The Table: Platform-Based Design
By Ed Sperling - 23 Apr, 2009 - Comments: 0

By Ed Sperling System-Level Design sat down with Simon Bloch, vice president and general manager of ESL/HDL Design and Synthesis at Mentor Graphics; Mike Gianfagna, vice president of marketing at Atrenta; and Jim Hogan, a private investor. What follows are excerpts of a lively, often contentious two-hour conversation.     SLD: Where does the consolidation happen in the chip design world... » read more

Experts At The Table: Platform-Based Design
By Ed Sperling - 09 Apr, 2009 - Comments: 0

By Ed Sperling System-Level Design sat down with Simon Bloch, vice president and general manager of ESL/HDL Design and Synthesis at Mentor Graphics; Mike Gianfagna, vice president of marketing at Atrenta; and Jim Hogan, a private investor. What follows are excerpts of a lively, often contentious two-hour conversation. SLD: Let’s start out with a point of reference before we get going on ... » read more

What Happens When We Hit Bottom?
By Ed Sperling - 02 Apr, 2009 - Comments: 0

The economy appears to have hit bottom. This is good news, but there are caveats.   First of all, not all industries will recover at the same rate. Communications never fully recovered from the dot-com bubble. Anyone who bet big on a communications recovery has either switched careers or retired. Now it looks as if the auto industry will be dragging for some time, and companies that hitche... » read more

What Works…And What Doesn’t
By Ed Sperling - 02 Apr, 2009 - Comments: 0

Lisa Su, chief technology officer at Freescale, talks about the future of system-level design, what's working and where the problems are. [youtube vid=zw5dUTuO7DY] » read more

Taming The Multicore Beast
By Ed Sperling - 27 Mar, 2009 - Comments: 0

By Ed Sperling Multicore chips are here to stay. Now what? That question is echoing up and down the ranks of tools vendors, design engineers, software developers and even among people who measure the performance and efficiency of semiconductors. There is now a Multicore Expo and a Multicore Association that includes a who’s who of electronics. And there are lots of working groups developing... » read more

Thinking Digital To Design Analog, And Vice Versa
By Ed Sperling - 27 Mar, 2009 - Comments: 0

By Ed Sperling Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome. Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with is... » read more

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