tag: system-level design

Time For Change
By Ed Sperling - 28 Jan, 2016 - Comments: 1

Semiconductor companies have been knocking on doors outside of the computer industry for the better part of two decades, pitching the value of digital and mixed-signal technology for improving efficiency in many market sectors. For most of that time, they received polite nods, occasional inquiries for more information and not much else. But over the past several years, those doors have open... » read more

Defining Sufficient Coverage
By Brian Bailey - 28 Dec, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the definition of sufficiency of coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"]; Larry Vivolo was, at the time of this roundtable, senior director of product marketing for [get... » read more

Who’s Profiting From Complexity
By Ed Sperling - 21 Dec, 2015 - Comments: 0

Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

Blog Review: Dec. 9
By Jesse Allen - 09 Dec, 2015 - Comments: 0

From spring-loaded knees to modular planes to a two-seater drone, there's a new world of transportation in this week's top engineering and technology picks from Ansys' Justin Nescott. As for disappearing worlds, check out the sun-like star getting eaten by a black hole. Cadence's Paul McLellan takes a look back at archaic terminology and even older standards, with a brief history of Calma to... » read more

Defining Sufficient Coverage
By Brian Bailey - 07 Dec, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the definition of sufficiency of coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"]; Larry Vivolo was, at the time of this roundtable, senior director of product marketing for [get... » read more

The Week In Review: Design/IoT
By Jesse Allen - 04 Dec, 2015 - Comments: 0

Tools Cadence uncorked the next generation of its custom design platform optimized for advanced 10nm FinFET designs. Features include multi-patterning and color-aware layout, electrically aware design, and module generator (ModGen)-based device array flow. Deals San'an IC will provide Mentor Graphics' design rule decks to its customers to help verify that their mobile and wireless gall... » read more

Shift In Focus For Low Power Design
By Alan Gibbons - 10 Sep, 2015 - Comments: 0

The increased levels of interest we have seen over the last couple of years in system-level power modeling and energy-aware system-level design methodology, coupled with broad participation in the associated industry standard activities around system level power, gives us a clear indication that a shift in focus for low-power design is taking place. Our attempts to deliver energy-efficient high... » read more

What Is A System Now?
By Ann Mutschler - 25 Jun, 2015 - Comments: 0

Defining a system used to be relatively straightforward. But as systems move onto chips, and as those chips increasingly are connected with applications and security spanning multiple devices, the definition is changing. This increases the complexity of the design process itself, and it raises questions about how chips and software will be designed and defined in the age of the [getkc id="76... » read more

Tech Talk: Power Tools
By Ed Sperling - 27 May, 2015 - Comments: 0

At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

Extending UPF For Use In System-Level Design
By Alan Gibbons - 12 Mar, 2015 - Comments: 0

Energy efficiency as a design constraint continues to dominate, and now that we see greater momentum behind a shift left toward system-level design, we are naturally seeing power-aware system-level design as a key area for EDA and IP enablement, especially among mobile and IoT platform providers. In my last article I highlighted the role that IP power models play in the architecture and design ... » read more

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