tag: SystemC

High-Level Design And High-Level Verification
By Dominik Strasser - 26 Sep, 2019 - Comments: 0

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

Week In Review: Design, Low Power
By Jesse Allen - 02 Aug, 2019 - Comments: 0

Rambus will acquire Northwest Logic, a maker of digital controller IP for memory, PCIe and MIPI. "Northwest Logic’s category-leading digital controllers fit perfectly with Rambus’ leadership portfolio of high-speed PHY solutions," said Northwest Logic president and CEO Brian Daellenbach. "This deal creates a one-stop-shop for SoC designers working on state-of-the-art applications across a b... » read more

Digital Twins Deciphered
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

Do Parallel Tools Make Sense?
By Brian Bailey - 10 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Dynamic Fault Injection For System-Level Simulation Of MEMS
By Fraunhofer IIS/EAS - 08 Aug, 2018 - Comments: 0

In this paper a method for dynamic fault injection and fault simulation as well as its application to MEMS based sensor systems is described. The prerequisite for this approach is the availability of accurate, but numerically efficient models for the MEMS element. Simulations based on SystemC and SystemC AMS are suitable to analyze the nominal behavior of complex sys- tems including electronics... » read more

Abstraction Aging
By Brian Bailey - 28 Jun, 2018 - Comments: 1

During the course of doing interviews for my article on system simulation and abstraction, I spoke to several people who, just like myself, had started their career pushing abstraction. At the time, we were all frustrated that the industry didn't move fast enough. The advantages of abstraction appeared to be so clear. Everyone developed slides showing that the cost to fix bugs increased the fur... » read more

The Week In Review: Design
By Jesse Allen - 15 Jun, 2018 - Comments: 0

M&A MIPS has reportedly been acquired again, this time by AI startup Wave Computing. Wave focuses on data center-based neural network training using its parallel dataflow processing architecture. In March, the company signed on to use 64-bit multi-threaded processor cores from MIPS in future projects. Previously, MIPS was owned by Tallwood Venture Capital, which acquired MIPS from Imaginat... » read more

Could Liquid IP Lead To Better Chips? (Part 3)
By Brian Bailey - 09 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Bulletproofing Virtual Prototypes
By Malte Doerper - 21 Dec, 2017 - Comments: 0

The big benefits of virtual prototyping methods are that they don’t rely on the availability of RTL or physical hardware. Instead they utilize modes of the future SoC. These models are typically lightweight and optimized for their use case, which is important in regards of simulation speed, modeling and testing effort. Model quality is a key concern, as the virtual prototyping end user accept... » read more

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