Unknown Signoff

By Graham Bell - 25 Apr, 2013 - Comments: 0

In last month’s blog, Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"], pointed out that the management of unknowns (X’s) in simulation has become a separate verification concern of signoff proportions. Modern power management schemes affect how designs are reset (start). X management and reset analysis are interrelated because many of the X’s in simulation come from unini... » read more

The Double Whammy

By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

Bringing Continuous Domain Into SystemVerilog Covergroups

By Various Writers - 26 Jul, 2012 - Comments: 0

This paper proposes a set of requirements for specifying functional coverage on an analog or mixed-signal block. We explain how the real number data type can be introduced in the [gettech id="31023" comment="SystemVerilog"] coverpoint specification and how it can enable a complete coverage specification for a mixed-signal verification environment. In discussing the requirements, we explore the... » read more

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tag: SystemVerilog

Unknown Signoff

The Double Whammy

Bringing Continuous Domain Into SystemVerilog Covergroups