Week In Review: Manufacturing, Test

By Mark LaPedus - 05 Oct, 2018 - Comments: 1

Chipmakers Fujitsu, once a major manufacturer of ICs, continues to move away from chip production. On Semiconductor has completed the incremental 20% share purchase of Aizu Fujitsu Semiconductor Manufacturing, Fujitsu’s 200mm wafer fab in Aizu-Wakamatsu. On Semi will now hold a 60% majority ownership in the fab joint venture. Consequently, the name of the venture will transition to On Semico... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 06 Apr, 2018 - Comments: 0

Trade wars China and the United States are in the midst of a trade war. Click here for the latest from CNN. Meanwhile, click here for a list of the winners and losers so far. Display Supply Chain Consultants, a research firm, provides more insights from a hi-tech perspective. Gary Shapiro, president and CEO of the U.S.-based Consumer Technology Association (CTA), issued a statement abo... » read more

TEL Sells Packaging Tool Unit

By Mark LaPedus - 04 Apr, 2018 - Comments: 0

Tokyo Electron Ltd. (TEL) has signed a definitive agreement to sell its packaging equipment unit, TEL NEXX, to ASM Pacific Technology. With the proposed deal, ASM Pacific enters some new markets. ASM Pacific sells wire bonders, pick-and-place systems, leadframes and other products. Established in 2001, TEL NEXX sells electrochemical deposition (ECD) and physical vapor deposition (PVD) s... » read more

Fan-Out Wars Begin

By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Packaging Challenges For 2018

By Mark LaPedus - 08 Jan, 2018 - Comments: 0

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Litho Options For Panel Fan-out

By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

Cheaper Fan-Outs Ahead

By Mark LaPedus - 07 Aug, 2017 - Comments: 6

Packaging houses continue to ramp up fan-out wafer-level packages in the market, but customers want lower cost fan-out products for a broader range of applications, such as consumer, RF and smartphones. So in R&D, the industry for some time has been developing next-generation fan-out using a panel-level format, a technology that could potentially lower the cost of fan-out. But there are ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer