tag: Teradyne

Detecting Spatial Blotches In Image Sensor Devices
By Christos Pantelidis - 12 Apr, 2022 - Comments: 0

One of the most common defects in image sensor devices is spatial blotches. The appearance of blotches in image sensors is a regular occurrence and may be generated by internal moving parts or may be moved by air currents within the camera. Composed of two main statistical methods, the first module employs an inferential method, applying a spatial segmentation of the current frame to obtain ... » read more

Site-To-Site Variation In Parallel Test
By Ed Seng - 16 Mar, 2022 - Comments: 0

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level te... » read more

Fundamental Shifts In IC Manufacturing Processes
By Ed Sperling - 14 Mar, 2022 - Comments: 2

High chip value and 3D packaging are changing where and how tests are performed, tightening design-for-reliability and accelerating the shift of tools from lab to fab. Heterogeneous integration and more domain-specific designs are causing a string of disruptions for chip manufacturers, up-ending proven fab processes and methodologies, extending the time it takes to manufacture a chip, and ul... » read more

Software-Driven and System-Level Tests Drive Chip Quality
By Bryon Moyer - 08 Mar, 2022 - Comments: 0

Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 25 Feb, 2022 - Comments: 0

Chipmakers, OEMs UMC plans to build a new fab next to its existing 300mm fab in Singapore. The new fab, called Fab12i P3, will manufacture wafers based on UMC’s 22nm/28nm processes. The planned investment for this project will be $5 billion. The first phase of this greenfield fab will have a monthly capacity of 30,000 wafers with production expected to commence in late 2024. To account fo... » read more

Unknowns Driving Up The Cost Of Auto IC Reliability
By Ed Sperling - 08 Feb, 2022 - Comments: 2

Automotive chipmakers are considering a variety of options to improve the reliability of ICs used for everything from sensors to artificial intelligence. But collectively they could boost the number of process steps, increase the time spent in manufacturing and packaging, and stir up concerns about the amount of data that needs to be collected, shared, and stored. Accounting for advanced pro... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 28 Jan, 2022 - Comments: 0

Government policy As reported, the United States is in dire need of more fab capacity as well as packaging plants. The U.S. took a big step in an effort to solve the problem. The U.S. House of Representatives this week introduced the America Competes Act of 2022. The bill includes funding for the Creating Helpful Incentives to Produce Semiconductors for America (CHIPS) Act, which is earmarked... » read more

The Gargantuan 5G Chip Challenge
By Ed Sperling - 11 Jan, 2022 - Comments: 0

Blazing fast upload and download speeds for cellular data are coming, but making the technology function as expected throughout its expected lifetime is an enormous challenge that will require substantial changes across the entire chip ecosystem. While sub-6GHz is an evolutionary step from 4G LTE, the real promise of 5G kicks in with millimeter-wave (mmWave) technology. But these higher-freq... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 23 Dec, 2021 - Comments: 0

Chipmakers TSMC has introduced another version of its 4nm process technology. The process, called N4X, is tailored for high-performance computing products. Recently, TSMC introduced another 4nm process, called N4P, which is an enhanced version of its 5nm technology. N4X is also an enhanced version of its 5nm technology. N4X, however, offers a performance boost of up to 15% over TSMC’s N5 pro... » read more

Speeding Up Scan-Based Volume Diagnosis
By Bryon Moyer - 07 Dec, 2021 - Comments: 0

In the critical process known as new-product bring-up, it’s a race to get new products to yield as quickly as possible. But the interplay between increasingly complex aspects of designs and process makes it difficult to find root causes of yield issues so they can be fixed quickly. Advanced processes have very high defectivity, and learning must be fast and effective. While progress has be... » read more

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