tag: Teradyne

Industry Standards For Chiplets And Their Role In Test
By Jeorge Hurtarte - 14 Jan, 2025 - Comments: 0

As the semiconductor industry increasingly moves to chiplets, 2.5D/3D packaging, and heterogeneous integration, there are significant new challenges for test. Leaders like Teradyne have the technologies necessary to respond and innovate, but to keep the industry running smoothly, we need effective collaboration, and that demands standardization. Source: Arizona State University There ... » read more

DFT At The Leading Edge
By Gregory Haley - 14 Jan, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed interfaces, and lifecycle data analytics, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; D... » read more

Shortcutting Graduates’ Path To Productivity In Manufacturing And Test
By Liz Allan - 16 Dec, 2024 - Comments: 1

Manufacturing, test, assembly, and analytics companies are finding unique ways to engage with universities in an effort to shore up the talent pipeline. The industry is recruiting graduates from universities across the U.S. while partnering with local institutes to serve specific needs. Industry/university co-operation includes: Mapping job descriptions Providing curricula frameworks... » read more

Semiconductor Test Faces Technology Shifts In The AI Era
By Jeorge Hurtarte - 10 Dec, 2024 - Comments: 0

The surge in data-rich applications shows no signs of slowing down, fueling significant evolution within the global semiconductor industry. This insatiable demand for data necessitates a comprehensive ecosystem involving sensors and systems to capture data, networks to transmit it, and storage and processing power to analyze it. Successful deployment of these applications relies on the devel... » read more

Silicon Lifecycle Management Gains Steam
By Laura Peters - 10 Dec, 2024 - Comments: 0

Silicon lifecycle management (SLM) is gaining significant traction, driven increasingly by stringent reliability requirements for safety-critical devices in aerospace, medical, and automotive. Improving reliability has been a discussion point for years, but it has become especially important with the use of chips designed at leading-edge nodes in both mission- and safety-critical application... » read more

Testing For Thermal Issues Becomes More Difficult
By Gregory Haley - 10 Dec, 2024 - Comments: 0

Increasingly complex and heterogeneous architectures, coupled with the adoption of high-performance materials, are making it much more difficult to identify and test for thermal issues in advanced packages. For a single SoC, compressing higher functionality into a smaller area concentrates the processing and makes thermal effects more predictable. But that processing can happen anywhere in a... » read more

Advanced Packaging Drives Test And Metrology Innovations
By Gregory Haley - 12 Nov, 2024 - Comments: 1

Advanced packaging has become a focal point for innovation as the semiconductor industry continues to push for increased transistor density and better performance. But the pace of change is accelerating, making it harder for the entire ecosystem to keep up with those changes. In the past, major developments were roughly on an 18-month to 2-year cadence. Today, this is happening every few mon... » read more

Yield Management Embraces Expanding Role
By Laura Peters - 12 Nov, 2024 - Comments: 0

Competitive pressures, shrinking time-to-market windows, and increased customization are collectively changing the dynamics and demands for yield management systems, shifting left from the fab to the design flow and right to assembly, packaging, and in-field analysis. The basic role of yield management systems is still expediting new product introductions, reducing scrap, and delivering grea... » read more

Balancing Parallel Test Productivity With Yield & Cost
By Anne Meixner - 12 Nov, 2024 - Comments: 0

Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

Silicon Carbide And Gallium Nitride Bring New Challenges For Semiconductor Test
By Jeorge Hurtarte - 12 Nov, 2024 - Comments: 0

In the era of megatrends such as electric vehicles (EVs), new technologies are emerging to keep up with evolving demands. One example of this is the evolution of compound semiconductors that use silicon carbide (SiC) and gallium nitride (GaN) for high-performance power systems. Innovating test protocols to handle wide bandgap materials For many power-related applications, the semiconductor in... » read more

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