Chip Industry Week in Review

By The SE Staff - 31 Oct, 2025 - Comments: 0

San Francisco-based Substrate raised more than $100 million to build a vertically integrated foundry that uses particle accelerators to produce "the world's brightest beams, enabling a new method of advanced X-ray lithography." The company claims its technology is comparable to ASML's high NA EUV, and notes it can extend well beyond 2nm. ASML has not publicly commented. The Nexperia chip sho... » read more

New Frontiers In Fault Detection And Classification

By Laura Peters - 14 Oct, 2025 - Comments: 0

IC manufacturers are increasingly relying on intelligent data processing to prevent downtime, improve yields, and reduce scrap. They are integrating that with fault detection and classification (FDC) to trace faults to their cause. Today’s FDC systems feature better sensors, variability control, and both predictive and prescriptive modeling. In the future, FDC will enable real-time decisio... » read more

Chip Industry Week in Review

By The SE Staff - 10 Oct, 2025 - Comments: 0

SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Chip Industry Week in Review

By The SE Staff - 03 Oct, 2025 - Comments: 0

Samsung and SK hynix joined OpenAI's Stargate initiative to ensure there will be enough memory chips to meet the needs of AI data centers. The goal is to produce up to 900,000 DRAM wafer starts per month. OpenAI also inked agreements to explore the development of next-gen data centers in Korea. Axcelis Technologies (ion implantation systems) will merge with Veeco Instruments (compound semic... » read more

Chip Industry Week in Review

By The SE Staff - 12 Sep, 2025 - Comments: 0

The U.S. is considering annual approvals for Samsung and SK hynix to export chipmaking tools and materials to their factories in China, replacing perpetual waivers granted under the validated end user system, reports Bloomberg. The proposal, presented by the U.S. Commerce Department to South Korean officials, would require the companies to reapply each year for specific quantities of restricted... » read more

Making The Most of Test Resources

By Laura Peters - 09 Sep, 2025 - Comments: 0

Semiconductor testing is undergoing multiple paradigm changes at once with the common goals of producing more known good die per month with low test cost. Achieving these goals requires a delicate balance between yield, quality, and test times. There are multiple ways to go about making better use of existing resources, many of which involve an increasing use of design for test (DFT) methods... » read more

The Hidden Cost Of Contact Resistance

By Gregory Haley - 09 Sep, 2025 - Comments: 1

Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

Infusing Trust Into The Supply Chain

By Anne Meixner - 09 Sep, 2025 - Comments: 0

An expanding supply chain of dies feeding multi-die products is prompting chipmakers to reassess and expand on ways to instill trust from end to end. This reaches deeper than just connecting disparate data. It requires integrating complex systems across vendors and protecting vendor data while instilling confidence in their customers and partners. Yet despite the time and effort that has bee... » read more

Transforming Test For Co-packaged Optics

By Laura Peters - 12 Aug, 2025 - Comments: 0

Data centers are undergoing a dramatic transformation to reduce the power consumption of high-speed data transmissions by 70% or more with co-packaged optics. By moving optical transceivers from the fronts of racks into the same package as the networking switch and HBMs, AI programs that used to take a week to run can now be completed in a day. To enable this change in production manufacturi... » read more

Chiplet Interfaces Embrace Failures

By Anne Meixner - 12 Aug, 2025 - Comments: 0

Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen. For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-f... » read more

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tag: Teradyne

Chip Industry Week in Review

New Frontiers In Fault Detection And Classification

Chip Industry Week in Review

Chip Industry Week in Review

Chip Industry Week in Review

Making The Most of Test Resources

The Hidden Cost Of Contact Resistance

Infusing Trust Into The Supply Chain

Transforming Test For Co-packaged Optics

Chiplet Interfaces Embrace Failures

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