Blog Review: Aug. 9

Tight design margins for 224G Ethernet; debugging mixed-signal partitioning issues; PCB digital prototype driven verification; getting light to a chip.


Synopsys’ John Swanson and Manmeet Walia note that designing for 224G Ethernet will entail some unique considerations, as design margins will be extremely tight, making it mission-critical to optimize individual analog blocks to reduce impairments.

Cadence’s Rick Sanborn finds that knowing how best to debug common partitioning-related issues and implicitly control them using common features of the mixed-signal elaborator can pull designers out of some tight spots.

Siemens’ Stephen Chavez argues that shifting left digital prototype driven verification of PCBs allows for quality to be built into a design rather than simply checking for quality after the fact.

Ansys’ Raha Vafaei notes that coupling electromagnetic light waves from a fiber to a chip is an intricate process, posing numerous challenges such as mode mismatch and alignment tolerances.

Keysight’s Brian Whitaker examines how temperature, age, and discharge rate affect battery run time and creates models to show the real-world impact of these effects on battery parameters.

In a video, Teradyne’s Tom Tran discusses how emerging markets are driving demand for high power discrete devices and why the increase in power makes the connection between device and tester increasingly important.

Arm’s Khaled Benkrid points to several new initiatives being undertaken to better align engineering education with the skills needed by the semiconductor and wider tech industry.

The ESD Alliance’s Bob Smith chats with CEMWorks’ Jonatan Aronsson and Cielo Gerrie about how system level electromagnetic simulation is becoming increasingly important in supporting the design of smart cities, next-generation transportation, and global communications systems.

And don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Onto Innovation’s Nick Keller and Andy Antonelli look at a non-destructive technique using the mid-infrared wavelength to measure the W recess in 3D NAND structures following the etching process.

National Instruments’ Paul Ulezko shows how low power validation contributes to a more environmentally conscious approach to manufacturing and boosts customer satisfaction by extending battery life.

Synopsys’ Gordon Cooper shows how to maximize the efficiency of AI accelerators and enable separation of tasks that require different ASIL levels.

Rambus’ Bart Stevens warns that all public key algorithm-based use cases leveraging RSA and ECC algorithms must be updated or replaced.

Winbond’s Craig Huang and Yulia Lee look at new opportunities for NOR flash as automotive electronics expand.

Renesas’ Sailesh Chittipeddi finds that a successful AI outcome depends on how educated your customers are about their own data sets.

Flex Logix’s Geoff Tate digs into the EFLX Gen2.4 update’s enhancements, including more clock resources and flexible BRAM.

Cadence’s Veena Parthan surveys a tool for automating repetitive CFD tasks and performing batch operations more efficiently.

Teradyne’s Mike Halblander takes a holistic approach to improving test equipment efficiency.

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