Complex Heterogeneous Integration Drives Innovation In Semiconductor Test


Heterogeneous integration is driving innovation in the semiconductor industry, but it also introduces more complexity in chip design, which translates to more intricate test requirements. The automated test equipment (ATE) industry is responding, developing and utilizing more sophisticated test equipment capable of handling the diverse functionalities and interfaces needed to test heterogeneous... » read more

Signals In The Noise: Tackling High-Frequency IC Test


The need for high-frequency semiconductor devices is surging, fueled by growing demand for advanced telecommunications, faster sensors, and increasingly autonomous vehicles. The advent of millimeter-wave communication in 5G and 6G is pushing manufacturers to develop chips capable of handling frequencies that were once considered out of reach. However, while these technologies promise faster ... » read more

Using AI To Glue Disparate IC Ecosystem Data


AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

How The Semiconductor Ecosystem Is Responding To Its Global Challenges


The semiconductor industry is changing rapidly, with government support for re-shoring capacity creating new interplay among resources in Asia, the U.S., and Europe—even as the industry develops and sustains new technologies like HBM and heterogeneous integration. Geopolitical factors such as the CHIPS (Creating Helpful Incentives to Produce Semiconductors for America) Act, the scarcity of s... » read more

Promises and Perils of Parallel Test


Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

AI/ML’s Role In Design And Test Expands


The role of AI and ML in test keeps growing, providing significant time and money savings that often exceed initial expectations. But it doesn't work in all cases, sometimes even disrupting well-tested process flows with questionable return on investment. One of the big attractions of AI is its ability to apply analytics to large data sets that are otherwise limited by human capabilities. In... » read more

Semiconductor Shifts In Automotive: Impact Of EV And ADAS Trends


The integration of advanced driver assistance systems (ADAS) and the transition towards electric vehicles (EVs) are significantly transforming the automotive industry. Modern vehicles, essentially computers on wheels, require substantially more semiconductors. In response, carmakers are forming stronger partnerships with semiconductor vendors – some are taking a page from tech giants like ... » read more

Driving Cost Lower and Power Higher With GaN


Gallium nitride is starting to make broader inroads in the lower-end of the high-voltage, wide-bandgap power FET market, where silicon carbide has been the technology of choice. This shift is driven by lower costs and processes that are more compatible with bulk silicon. Efficiency, power density (size), and cost are the three major concerns in power electronics, and GaN can meet all three c... » read more

Chip Industry Week in Review


Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Delivering On Power During HPC Test


The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

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