Using AI To Glue Disparate IC Ecosystem Data


AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

Optimizing Wafer Edge Processes For Chip Stacking


Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

Legacy Process Nodes Are Critical To Many Industries


As the semiconductor industry continues to push the boundaries of innovation with advanced nodes, it is easy to overlook the critical role that ICs manufactured at legacy process nodes play in our everyday lives. While the spotlight often shines on the leading-edge advancements of 5nm technology and below, it’s the mature nodes, those above 28nm and even above 130nm, that are the unsung ch... » read more

New Materials Are in High Demand


Materials suppliers are responding to the intense pressures to improve power, performance, scaling, and cost issues, which follows a long timeline from synthesis to development and high volume manufacturing in fabs. The advances in machine learning help present a wide field of candidates, which engineers then narrow to potential use. When building standard logic semiconductor chips, the prim... » read more

3.5D: The Great Compromise


The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Legacy Process Nodes Going Strong


While all eyes tend to focus on the leading-edge silicon nodes, many mature nodes continue to enjoy robust manufacturing demand. Successive nodes stopped reducing die cost at around the 20nm node. “In the finFET era of processes, esoteric process requirements necessary to move technology forward with each generation have added significant cost and complexity,” explained Andrew Appleby, p... » read more

Single Vs. Multi-Patterning Advancements For EUV


As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Precise Control Needed For Copper Plating And CMP


Chipmakers are relying on machine learning for electroplating and wafer cleaning at leading-edge process nodes, augmenting traditional fault detection/classification and statistical process control in order to extend the usefulness of copper interconnects. Copper is well understood and easy to work with, but it is running out of steam. At 5nm and below, copper plating tools are struggling to... » read more

AI: Great, But Somehow Still Not Very Good


In an invited presentation at CS Mantech 2024, Charlie Parker, senior machine learning engineer at Tignis, provides context for the AI hype cycle with a high-level overview of machine learning concepts, then explores how the technology fits into the fab, from inventory management to institutional knowledge capture, but warns that it is worth being aware of the ways in which machine learning mod... » read more

Chip Industry Week In Review


Rapidus and IBM are jointly developing mass production capabilities for chiplet-based advanced packages. The collaboration builds on an existing agreement to develop 2nm process technology. Vanguard and NXP will jointly establish VisionPower Semiconductor Manufacturing Company (VSMC) in Singapore to build a $7.8 billion, 12-inch wafer plant. This is part of a global supply chain shift “Out... » read more

← Older posts Newer posts →