tag: TLM-2.0

Rethinking Models
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ed Sperling The move to future process nodes will require more than just new materials, better layouts and higher levels of abstraction. It also will require a fundamental re-thinking of how high-level architectural models are created and what’s included in them. While the Transaction-Level Modeling (TLM) 2.0 standard has provided significant improvements for everything from layout to ... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

Verifying Low-Power Designs
By Ed Sperling - 14 Jan, 2010 - Comments: 0

By Ed Sperling Power islands and multiple voltages used to be reserved for cell phone and process companies, but as more companies move to 65nm and 45nm process nodes these approaches to saving power—particularly in chips with multiple cores—are becoming mainstream. The problem isn’t in the architecture of the chips, although that certainly brings its own set of challenges. More and m... » read more

Experts At The Table: Rising Complexity Meets Verification
By Ed Sperling - 10 Dec, 2009 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are ... » read more

End-User Report: Interoperability Still Lacking With System-Level Power Modeling
By Ann Mutschler - 27 Aug, 2009 - Comments: 0

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling. By Ann Steffora Mutschler SLD: How long has N... » read more

Trends in System-Level Prototyping
By Various Writers - 27 Mar, 2009 - Comments: 0

By Clive Maxfield One problem with electronics is that certain terms can mean different things, depending on who one is talking to at the time. Even worse, some terms have a tendency to evolve over time. This means that when we are presented with a topic like "Trends in System-Level Prototyping," before leaping headfirst into the fray, it may be a good idea to first define exactly what we mean... » read more

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