tag: UC Berkeley

Tech Talk: Faster But Less Accurate
By Ed Sperling - 25 Oct, 2012 - Comments: 0

Semiconductor Engineering talks with professor Jan Rabaey of the University of California at Berkeley about new design approaches that could significantly boost performance and simplify design and verification—for some applications. [youtube vid=hAk1xA56h_A] » read more

Quiet, Steady And Sometimes Unexpected Advances For SOI
By Ed Sperling - 20 Sep, 2012 - Comments: 0

By Ed Sperling After years of talking about equivalent pricing, technical advantages and consistent processes, silicon on insulator finally appears to be making significant inroads—but not necessarily in ways, places, or even at process nodes where it initially was predicted to gain ground. What’s driving at least some of this change is the semiconductor industry’s progression toward ... » read more

The Trouble With FinFETs
By Joanne Itow - 16 Aug, 2012 - Comments: 0

By Joanne Itow The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge. In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was �... » read more

What Comes After FinFETs?
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm. The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next-generation candidates that could o... » read more

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 29 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 22 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Da... » read more

Efficiency Vs. Accuracy
By Barry Pangrle - 14 Jun, 2012 - Comments: 0

By Barry Pangrle If all you have is a hammer, everything looks like a nail. I wrote an article, Power vs. Accuracy, last year that discussed tradeoffs between power and accuracy for different applications. It turns out that for a number of processing applications, if every bit isn’t perfect, the impact on the final result might not be all that great. Anyone performing financial analytical... » read more

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond
By Various Writers - 30 May, 2012 - Comments: 0

The following is a special guest post by Dr. Chenming Hu, TSMC Distinguished Professor at UC Berkeley. He and his team published seminal papers on FinFETs (1999) and UTB-SOI (2000). This post first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  ~~ The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations ... » read more

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